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Home  > ADVANCED PACKAGING: 3D IC, WLP & TSV
  > Advanced Packaging: 3D IC, WLP & TSV
 
  >  TOP STORY
Following the ITRS roadmap with CMOS downscaling is the traditional way to proceed. But the R&D expenses to sustain such a roadmap are extremely selective. Only a few companies or consortia can afford it. That’s why advanced CMOS technology could start to be seen as a kind of commodity and integration with new solutions appears as a much stronger differentiator element. Packaging contributions...

 
  >  ANALYSIS
Why are fan-out wafer-level packages (WLP) one of the hottest topics in the advanced packaging arena these days? The short answer is that they enable thinner, smaller packages.One of the most well known examples of a fan-out WLP structure is Infineon’s (www.infineon.com; Neubiberg, Germany) embedded wafer-level ball grid array (eWLB) technology. This technology uses a combination of front- ...

 
  >  INTERVIEW
Wafer level cameras represent a tantalising opportunity to substantially decrease the cost and form factor of solid state camera modules. After many years of endeavour, successful integration of the technologies necessary to manufacture true wafer level cameras was announced in 2007. While there is great potential for these cameras on mobile platforms, OEMs are reluctant to design-in product ...
 

 
  >  REVERSE ENGINEERING
In a word, Sony’s new backside illuminated image sensor process can be described as exotic.  The obvious highlights are the conventional CMOS process run on a sacrificial SOI starting wafer, the wafer bonding techniques for the carrier wafer, and the backside wire bonding – but the innovation doesn’t stop there.  This device uses three types of isolation, unconventional liners on the ...
 

 
  >  PRESENTATION
Please download Jean-Christophe Eloy's presentation – EMPC Keynote June 2009, at Rimini (Italy) ...

 
  >  LATEST REPORT
How 3-D integration will challenge and reshape the memory industry?...

 
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  >  NEWSLETTERS
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New
 July 2009

 
  >  NEWS
Alchimer S.A., a leading provider of cost-saving wet deposition processes for ...

As part of this non-exclusive agreement, SUSS MicroTec becomes an authorized equipment ...

The compact dimension of the LSI is achieved by using a single power supply (1.8V) ...

Wafer level packages remain one of the highest growth semiconductor packages due to ...

Producing thousands of lenses simultaneously on a single wafer using technology ...

Producing thousands of lenses simultaneously on a single wafer using technology ...

The great potential of 3D technologiesOver the past few years, system designers and ...

The ADP2108 dc-dc converter from Analog Devices is designed to provide better energy ...

Alchimer's eG ViaCoat is a wet deposition process for the copper seed metallization of ...

STS announced that the company has received an order from Fraunhofer Institute for ...

EPCOS is utilizing EVG's wafer bonder to manufacture surface acoustic wave (SAW) ...

People have been saying for years that we have reached the limit of Moore's Law.
In a word, Sony’s new backside illuminated image sensor process can be described as ...

austriamicrosystems business unit Full Service Foundry today announced the availability...

The new offering is the latest in the HD-8900 low-cure PBO series and combines the ...


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