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Home  > ADVANCED PACKAGING: 3D IC, WLP & TSV
  > Advanced Packaging: 3D IC, WLP & TSV
 
  >  TOP STORY
3D Integration for wireless products: An industrial perspective
Following the ITRS roadmap with CMOS downscaling is the traditional way to proceed. But the R&D expenses to sustain such a roadmap are extremely selective. Only a few companies or consortia can afford it. That’s why advanced CMOS technology could start to be seen as a kind of commodity and integration with new solutions appears as a much stronger differentiator element. Packaging contributions...
 
 
  >  ANALYSIS
Demand for Fan-Out Wafer-Level Packages Catch On
Why are fan-out wafer-level packages (WLP) one of the hottest topics in the advanced packaging arena these days? The short answer is that they enable thinner, smaller packages.One of the most well known examples of a fan-out WLP structure is Infineon’s (www.infineon.com; Neubiberg, Germany) embedded wafer-level ball grid array (eWLB) technology. This technology uses a combination of front- ...
 
 
  >  INTERVIEW
The Wafer Level Camera Juggernaut
Wafer level cameras represent a tantalising opportunity to substantially decrease the cost and form factor of solid state camera modules. After many years of endeavour, successful integration of the technologies necessary to manufacture true wafer level cameras was announced in 2007. While there is great potential for these cameras on mobile platforms, OEMs are reluctant to design-in product ...
 
 
  >  REVERSE ENGINEERING
Sony Backside Illuminated (BSI) CMOS Image Sensor
In a word, Sony’s new backside illuminated image sensor process can be described as exotic.  The obvious highlights are the conventional CMOS process run on a sacrificial SOI starting wafer, the wafer bonding techniques for the carrier wafer, and the backside wire bonding – but the innovation doesn’t stop there.  This device uses three types of isolation, unconventional liners on the ...
 
 
  >  PRESENTATION
Overview of Packaging Technologies & Markets
Please download Jean-Christophe Eloy's presentation – EMPC Keynote June 2009, at Rimini (Italy) ...
 
 
  >  LATEST REPORT
Memory Applications, Packaging & Integration Trends 2009
How 3-D integration will challenge and reshape the memory industry?...
 
 
  >  EVENTS
SEMATECH Workshop on 3D Interconnect Metrology
...
 
 
  >  NEWSLETTERS
Download our latest newsletters

New
 July 2009

 March 2009
 
 
  >  NEWS
June 23rd 2009
Alchimer S.A., a leading provider of cost-saving wet deposition processes for ...

June 22nd 2009
As part of this non-exclusive agreement, SUSS MicroTec becomes an authorized equipment ...

June 17th 2009
The compact dimension of the LSI is achieved by using a single power supply (1.8V) ...

June 17th 2009
Wafer level packages remain one of the highest growth semiconductor packages due to ...

June 16th 2009
Producing thousands of lenses simultaneously on a single wafer using technology ...

June 16th 2009
Producing thousands of lenses simultaneously on a single wafer using technology ...

June 15th 2009
The great potential of 3D technologiesOver the past few years, system designers and ...

June 15th 2009
The ADP2108 dc-dc converter from Analog Devices is designed to provide better energy ...

June 15th 2009
Alchimer's eG ViaCoat is a wet deposition process for the copper seed metallization of ...

June 12th 2009
STS announced that the company has received an order from Fraunhofer Institute for ...

June 8th 2009
EPCOS is utilizing EVG's wafer bonder to manufacture surface acoustic wave (SAW) ...

June 8th 2009
People have been saying for years that we have reached the limit of Moore's Law.
June 3rd 2009
In a word, Sony’s new backside illuminated image sensor process can be described as ...

May 27th 2009
austriamicrosystems business unit Full Service Foundry today announced the availability...

May 22nd 2009
The new offering is the latest in the HD-8900 low-cure PBO series and combines the ...


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