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  February 9th - 07:24 am
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Home  > ADVANCED PACKAGING: 3D IC, WLP & TSV
  > Advanced Packaging: 3D IC, WLP & TSV
 
  >  TOP STORY
Samsung presents new 3D TSV Packaging Roadmap
Everything really started on April 2006 and later on April 2007 when Dr Chang-Gyu - Samsung's Hwang President & CEO - announced the company intention to commercialize 3D TSV stacked NAND Flash memory and 3D TSV stacked DRAM memory.  Talking about 3D silicon integration at that time, Dr ...
 
 
  >  ANALYSIS
Via first, middle, last, or after?
In case you aren’t already confused enough trying to follow the debate about making TSVs using a via first or last process, it’s now more a question of using via first, middle, last, or after bonding. Or all of them....
 
 
  >  INTERVIEW
NEC Schott introduces Glass Substrates with Hermetic Metal Through Vias for WLP of MEMS & Sensor applications
NEC SCHOTT Components Corporation, established in Sept 2000, is a joint venture company between Japanese electronics and computer corporation NEC and SCHOTT. The core technologies are glass-to-metal and ceramic-to-metal sealing, thermal sensing components as well as a variety of cutting edge specialty glass competences. With 1,500 employees at five production locations and several competence ...
 
 
  >  REVERSE ENGINEERING
The Evolution of Three-Axis MEMS Inertial Sensor Packaging – Size Does Matter!
Chipworks has been monitoring the MEMS inertial sensor market for several years. In 2002 we did an analysis of the STMicroelectronics LIS2L02AS two axis accelerometer, which came in a 15.5 mm x 7.5 mm x 2.5 mm thick SO-24 package, shown in Figure 1. The MEMS and ASIC were wire bonded together and mounted side-by-side in the package, as indicated in Figure 2. A simple calculation shows that the ...
 
 
  >  PRESENTATION
3D TSV Market and Technology update
Please download Jean-Christophe Eloy's presentation – EV Group’s webcast, Sept. 17 ...
 
 
  >  LATEST REPORT

3D IC & TSV Interconnects 2010
(bundle of 2 reports)
...
 
 
  >  EVENTS
MEPTEC - From chip to system: Design challenges & solutions
This one-day symposium addresses critical challenges facing today's EDA companies, as they are called to bridge the design gaps from silicon to package, and board to system. Setting the course for the day will be keynote speaker, Tom Gregorich, VP of IC package engineering at Qualcomm, who will discuss the concept of "concurrent design" in his presentation titled Design Challenges and Solutions ...
 
 
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 December 2009

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  >  NEWS
February 5th 2010
Through Silicon Via technology is known to offer numerous advantages: application and ...

February 4th 2010
In a deal that will generate economical new process options for the 3D integration ...

February 4th 2010
Under the parties' confidential agreements, Freescale and EPIC have licensed each ...

February 2nd 2010
TowerJazz and Soitec announced today that they have signed an agreement that will ...

February 2nd 2010
ISE 2010 will return for the 3rd time ...

February 2nd 2010
Mr Or-Bach previously pioneered ASICs at eASIC and later at Chip Express. Last year, ...

February 1st 2010
Intel recently commented that it is still exploring the future use of 3D devices based ...

January 28th 2010
Cascade Microtech, Inc. (NASDAQ: CSCD), a worldwide leader in the precise electrical ...

January 28th 2010
Dresden is the Saxony state capital and is an attractive and energetic modern city ...

January 27th 2010
Tezzaron is readying new 3-D devices, including a 4-gigabit DRAM product. This 100-nm ...

January 26th 2010
Applications for this type of sensors include cell-phone and notebook webcams which are...

January 21st 2010
The publication of the article began with a discussion between Borel and EDA ...

January 21st 2010
Presto Engineering Inc., the pioneer of the labless business model for semiconductor ...

January 21st 2010
Leti, a leading global research center committed to creating and commercializing ...

January 21st 2010
ICAP Ocean Tomo, the intellectual property brokerage division of ICAP Plc  ...


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