Home  > ADVANCED PACKAGING
  > Advanced Packaging: 3D IC, WLP & TSV
 
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At its Fab 8 campus in Saratoga County, NY, the company has begun installation of a special set of production tools to create Through-Silicon Vias (TSVs) in semiconductor wafers processed on the company’s leading-edge 20nm technology platform. The TSV capabilities will allow customers to stack...


 
  >  ANALYSIS
Wafer-level chip-scale packages (WLCSPs) are by no means the lowest-cost solution available, but its tiny volume and electrical performance benefi ts are turning it into the “go-to” package for use in mobile phones and tablets....

Source: 3D Packaging Feb. 2012 – Powered by Yole Développement

 
  >  INTERVIEW
ERS is a German company, founded in 1970 and specializing in thermal solutions for the semiconductor industry. Calling itself a “research & development company with a large production capacity” ERS participates actively in semiconductor industry events and welcomes thermal challenges that defy standard solutions. In 2008, engineer Klemens Reitinger took over the company from its founder Erich ...
 

 
  >  REVERSE ENGINEERING
Whether it’s for the main camera of low-cost phones or the front-facing camera of high-end phones, low-cost, low-resolution camera modules are extremely important....

Source: 3D Packaging Feb. 2012 - Powered by Yole Développement
 

 
  >  LATEST REPORT
The number of wafers processed with DRIE will see 5X growth 2011 – 2017...
 

 
  >  PRESENTATION
Feel free to download Jean-Marc Yannou's presentation held at the 7th European Advanced Technology Workshop on Micropackaging and Thermal Management ...

 
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The Connect in 3D Collaboration Summit is an unprecedented networking event engineered for the global supply system dedicated to 3D integration of IC chips in devices. Not just another meet-and-greet, this is a powerful, innovative game-changing event for networking and collaboration. Connect in 3D provides a two-day platform to meet, learn, talk, and ultimately collaborate in a time-efficient and ...

 
  >  TRADE SHOWS & CONFERENCES
This workshop will focus on low-temperature bonding technologies which will ultimately lead to entirely new manufacturing approaches to 3D and heterogeneous integration of semiconductor devices and microsystems, as well as photonic systems. ...
 
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  >  NEWS
Typical encapsulation technologies include: glob top, underfilling, transfer molding ...

Yole Développement announces its report “Polymeric Materials for 3DIC ...

“3D IC test wafers will run this year and high-volume 3D IC manufacturing will ...

Here, at the junction of advanced design, process technology and state-of-the art ...

If you think of SoC silicon as a stack, the lowest layer is where you'll find the ...

Carsem has successfully assembled and qualified High Brightness Silicon Substrate LED ...

Last October, memory rivals Samsung and Micron announced the creation of a consortium ...

Only a smattering of 2.5D/3D chips have been announced and shipped in the market today....

Even before finFETs, there are also questions about the 20nm node at the foundries. And...

Today nearly all electronic devices are built on complementary metal-oxide ...

"3-D affords the capability of integrating FPGAs with ASICs, with memory with ...

Drawing the analogy of the human brain, the company's niche buffer memory products act ...

SunPower invested an undisclosed amount of capital in Deca when the packaging house ...

The IC industry must embrace — and become more active — in the standards ...

ChipMOS has set aside a 2012 capex budget of NT$2 billion (US$67.8 million), with 70% ...

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