Accurate electrical and manufacturing modeling is highly desirable for the design of 3-D stacks, in which one of the biggest concerns is thermal management. And one of the deciding factors in the timing of true through-silicon via (TSV) technology really taking off is likely to be the existence - or lack - of 3-D EDA tools.

Makers of multicore microprocessors and cell phones are among those with the most immediate need for 3-D. IBM’s (Armonk, NY; www.ibm.com) general technology interests, for example, continue to be in the area of servers, ASICs, and complementary spaces such as game-console processors, according to Jason Hibbeler, an EDA engineer at IBM. IBM also has a silicon-germanium amplifier product that uses TSV technology.

Tool development
It appears that most of the large EDA tool suppliers don’t have 3-D EDA tools available yet, according to Patrick Leduc, who coordinates development of 3-D integration processes for CMOS circuits at CEA-Léti Minatec (www.cea.fr; Grenoble, France). One small company, however, Leduc points out, already has a 3-D EDA tool ready.  R3Logic (Waltham, Mass.; www.r3logic.com) unveiled a 3-D EDA tool last year—a layout editor that allows you to do 3-D mask layout for full custom design—and is actively developing other tools.

R3Logic is in the business of writing CAD tools for 3-D and, although they don’t do a thermal solver themselves, they’re exploring ways to take data and put it into the interface for thermal solvers. As a member of a U.S. Department of Defense Advanced Research Projects Agency (DARPA) team since 2004, R3Logic is working with partners at Parametric Technology Corp. (Needham, Mass.; www.ptc.com), Irvine Sensors (Costa Mesa, Calif.; www.irvine-sensors.com), as well as collaborators at North Carolina State University (NCSU; Raleigh, NC.; www.ncsu.edu) and the University of Minnesota (Minneapolis, Minn.; www.umn.edu), to address heat issues.

“NCSU has developed a number of algorithms to extract data to create macromodels, and the University of Minnesota is studying thermally aware 3-D placement algorithms,” says Lisa McIlrath, chief executive officer, founder, and president of R3Logic. “Scale is a big problem when trying to solve thermal issues in a chip. When you look at how thermal issues will affect a circuit inside the chip, you need to look at it in very fine scale. Then you need to determine which thermal issues you’re concerned about—whether it’s the chip melting or the device behaving badly. The latter is more of a problem with analog circuits and RF, since the beta of the transistor is exponentially related to the temperature. A transceiver can stop working if it overheats, for example. Those issues need to be viewed down at the transistor level. Other issues to consider include whether or not the chip will delaminate if overheated and how to deal with cooling. There are many different levels of thermal problems and each is important in its own domain.”

NCSU’s macromodeling work essentially takes the chip and divides it into a small grid, then extracts a thermal model for each of the small grid elements. This allows scaling from coarse to fine resolution. And the University of Minnesota is working on automatically adjusting the placement of circuits, based on thermal concerns, as well as also trying to figure out how to distribute thermal vias to provide some heat removal.

“With thermal-aware placement, NCSU can adjust portions of the circuit so a number of things generating heat aren’t put on top of each other. They’ve shown, at least theoretically, that they can mitigate the heat problem considerably. What we’re working on—in development right now—is a flow for 3-D in which you can do the design, floor-planning, and then feed into other tools to do the 2-D placement and routing,” says McIlrath. “Hopefully this will be ready in about a year. We’re working on a way to take the data, use the NCSU macromodels, and feed it into a thermal solver (a finite element analysis solver), and also feed in with it the power models that are extracted for each circuit level. With the reports from this analysis, we allow adjustments based on timing closure and thermal issues.”

Cadence Design Systems Inc. (San Jose, Calif.; www.cadence.com) is also working on 3-D EDA tools, and has been closely tracking the 3-D design tool area since about 2001. “We’re focusing on the first level of issues that people are going to run into,” says Ted Vucurevich, Cadence’s chief technology officer. “Those are the issues of doing analysis, whether it’s electrical or thermal, across the layers of the 3-D stacks. Many times these stacks are made from different process technologies. Most EDA tools today have a built-in assumption of a single technology being represented. What happens in a stack where I have multiple technologies? There are basic issues associated with being able to set up and perform the types of analysis you’d like to do on a 3-D stack either during design or for signoff verification purposes. Another area of focus is enabling efficient physical planning of the 3-D stack. Yet another area of interest is test. Once the die are stacked, you have a huge test challenge. Are you going to stack, then do final test with a reconfigurable ability to fix things that didn’t work? Or is your strategy to test layer by layer? These areas are either completely unexplored or are in early exploration.”

And IBM has developed an extensive suite of tools for chip and package design and analysis. “We’re extending our existing tools and methodology to handle 3-D structures in a way that will require only incremental additional development,” says Hibbeler.