Defining 3-D WLP MEMS

There are many interpretations of what exactly 3-D WLP MEMS means. Yole, for starters, defines it as the stacking at the wafer-level of MEMS and other type of die, using through-silicon vias (TSVs) as interconnects.

From the perspective of a leading designer and manufacturer of silicon capacitive acceleration and pressure sensors, VTI Technologies (Finland; www.vti.fi) says that 3-D WLP MEMS is an assembly process in which an IC die and a MEMS die are combined on the wafer level. “This means either chip-to-wafer or wafer-to-wafer,” explains Heikki Kuisma, VTI’s director of MEMS concept development.

And Dalsa (Waterloo, Ontario, Canada; www.dalsa.com), a leader in high-performance digital imaging and semiconductors, which also provides semiconductor wafer foundry services for use in MEMS, defines 3-D WLP MEMS as products that include the MEMS device and the control electronic ASIC, where assembly, interconnections and test are done at the wafer-level—prior to singulation.

Gilleo recognizes two distinct levels of MEMS WLP, but points out that there can be subdivisions within each. “The first level is pre-packaging WLP, which is typified by ‘capping.’ A wafer cap is usually produced from silicon. It’s often more complex than a simple etched-out recess because double-singulation is usually needed to expose the bonding pads on the active MEMS wafer,” he explains. “But the capped wafer, while protected, is not yet a package and the chip is now ready for traditional ‘electronic’ packaging that can include wire bonding and overmolding. Alternatively, the capped device can be placed in a non-hermetic injection molded plastic package. Both methods are commercial.”

The next level is full WLP, where the entire package is completed at wafer-level (or at least all of the critical steps are); bumping of the WLP, for example, could be done at a later stage or at a different facility. “There are several strategies to consider,” says Gilleo. “While environmental protection may be relatively easy to achieve using WL processes such as capping, producing the electrical interconnect is more challenging - especially if you want to maintain hermeticity. The electrical path can be either through the MEMS device (a TSV), or through the cap (in which case the cap becomes the bottom of the package), or around the edge of the chip or cap. At this stage, it is unclear which strategy, if any, will dominate.”

While the WLP can be produced by bonding a cap and MEMS wafer, there are alternatives, Gilleo says, such as integral caps, where a 3-D cap is created in place directly on the MEMS wafer without wafer bonding. A sacrificial structure can be produced over the area to be protected, followed by deposition of the “package” by metallization or another deposition technique. The sacrificial material is etched away so that the etchant enters through one or more small openings in the cap/cover material. Then the final step is to evacuate the resulting chamber and seal the opening or openings. Or the opening might be connected to a microtube for sampling.

Market drivers

What’s the general consensus on what’s driving the market? “Size and cost are the primary market drivers for 3-D MEMS,” says Kuisma. “The target applications are devices for consumer electronics such as sensors, frequency sources, and RF devices.”

Dalsa’s Donald Robert, vice president of sales and marketing, agrees. “The main drivers for 3-D MEMS are the requirements for smaller package size and lower costs,” Robert says. “Although a 3-D MEMS approach provides an inherently smaller package, it can be cost-effective only when the die size of the control electronic ASIC and MEMS device are similar, to minimize an unused area on the wafer containing the smaller die size. Or when the yield of each of the MEMS and ASIC are high, since the yield of the 3-D MEMS product will be: MEMS device yield x ASIC yield x 3-D assembly yield.”

The wafer diameter of the MEMS device and ASIC is also an important factor, Robert points out. “Today, the majority of MEMS devices are still manufactured on 150-mm wafers, where the majority of control electronic ASIC are done on 200-mm wafers,” he says. “The majority of 3-D MEMS will have to be done on 200mm over the next few years. To build Dalsa’s leadership in the market, we’ll begin implementing our MEMS technology portfolio on a new 200-mm MEMS manufacturing line at our Bromont, Quebec, Canada facility. Portable consumer devices such as cell phones and PDAs are the key market drivers, leading to requirements for increased functionality and a smaller footprint. Inertial sensors such as accelerometers and gyros and RF MEMS are target applications for 3-D MEMS.”

Gilleo thinks accelerometers continue to be the most “valuable and versatile player” and there’s no end in sight. “We should thank Steve Jobs at Apple (Cupertino, Calif.; www.apple.com) for doing the obvious for the iPhone and the iTouch with clever integration,” he says. “If we look at all the steps required for using a passive cap (no TSVs), it’s painful. The ADI process, for example, requires careful sawing of the cap wafer to remove parts of the wafer that would cover the wire bonding pads. And after all of these WL steps, you still need to do the real packaging. MOEMS are another good candidate for WLP, but the need for optical paths is more problematic—especially when dealing with thermomechanical issues. Motion-sensing MEMS will be the first area to widely adopt full WLP, and I’ve found hundreds of patents and applications in this field, so we’re close to implementation.”

Technical challenges

As far as technical challenges for 3-D WLP MEMS, it appears the issues can be classified more as cost related and strategic ones than purely technical hurdles.

“MEMS wafers are different than IC wafers, for which the WLP specifications have been developed. Adaptation is often needed. The technical requirements can’t be easily generalized. Vias for ICs may have too large parasitics for MEMS. The MEMS may be too thick for vias (hundreds of microns),” Kuisma points out.

The main challenges of 3-D MEMS are cost related ones, according to Robert. “Current available technologies for TSV formation and filling are too expensive and, combined with access to low labor cost, die-level assembly houses, it prevents the rapid adoption of 3-D WLP MEMS,” he adds. “By working closely with our suppliers, we have been able to improve the DRIE throughput and filling technology so that 8-10:1 aspect ratio TSVs can be made and filled at reduced costs, but still, for most applications, the outcome is that if the 3-D approach cannot provide a 20 to 30% die size reduction, a die-level co-package approach is likely cheaper. Very few applications are willing to pay a premium for a smaller package. We are working on new materials and new technologies to significantly reduce the cost associated with TSVs.”

And the MEMS community should probably take credit for inventing TSVs, Gilleo says. “It’s noteworthy that the Bosch process, which appears to have been developed and adopted first by MEMS fabs, is one of the foremost for ‘pure’ electronics TSVs,” he says. “In my opinion, several MEMS fabs have all the necessary processes to form TSVs through the MEMS or capping wafers. There are a number of strategic issues rather than technical obstacles, such as where to apply the TSV. Should it be through MEMS or through cap? A TSV cap seems like an obvious choice, but then the cap wafer must be electrically connected to the MEMS wafer, so is this more challenging than MEMS TSV where the connection can be direct? But the resulting package will be very small, likely chip size. While MEMS have few packaging standards, with too much application and device specificity, this might be an issue that requires retooling of PCBs along with some new assembly concerns.”

Interconnecting MEMS & ICs

There are many methods to create a close interconnect between MEMS and ICs. Which approach or approaches will go mainstream has yet to be determined.

Kuisma doesn’t expect to see the integrated MEMS approach (having the IC and MEMS on the same chip) become mainstream. “From a logistic perspective, MEMS-last may be possible, but the area waste in both IC and MEMS process will increase the cost and will need to include the IC under the cap wafer. The established QFN and LGA overmolded packaging is the real competitor for 3-D WLP MEMS,” he says.

“We have nothing against integrated MEMS!” declares Robert. “This is a key advantage we have over most of our MEMS foundry competitors. We make integrated MEMS and also understand very well the constraints of CMOS-MEMS integration. In fact, a significant portion of the products we manufacture today are monolithically integrated and are all made at DALSA.” However, wafer fabrication requirements for the ASIC and MEMS are evolving in quite different ways, according to Robert. Several years ago, Dalsa decided to focus its investments in MEMS and work with third-party CMOS foundries for the control electronic portion of the product. The most typical flows are MEMS over CMOS (above IC). MEMS ‘before’ or ‘in the middle’ are less popular approaches, he says, because most foundries do not allow pre-processed wafers in their fabs, due to contamination issues. Dalsa also makes wafer-level bonding of the MEMS device over the CMOS wafer that may or may not be included in the final packaging. In keeping with the trend of moving to smaller geometry/higher mask count, Dalsa expects the number of products using MEMS over CMOS to decrease as the total mask count (CMOS and MEMS) would make these products economically viable. Also, thermal budget requirements of the MEMS process may not be compatible with an advanced CMOS process, making wafer-level bonding of MEMS with CMOS or 3-D WLP MEMS a good alternative, as long as die size are similar.

Gilleo believes that MEMS microphones are probably the place to look for issues and answers. “Knowles Electronics (Itasca, Illinois; www.knowles.com) uses a multichip package strategy. The MEMS microphone and amplifier are kept separate. This likely provides maximum versatility and the highest yield; microphones are challenging because the moving diaphragm must be nearly perfect,” he says. “But Akustica (Pittsburgh, Pennsylvania; www.akustica.com) decided to integrate the microphone and electronics onto a single chip. Each company seems to be doing well, so maybe there isn’t a ‘best’ strategy.”

Gilleo also points out that Analog Devices Inc. (Norwood, Mass.; www.analog.com) integrated accelerometer mechanics and electronics many years ago, but not everyone agrees this is the way to go. “So should the electronics be formed on the MEMS wafer, which requires a CMOS process, or kept separate as seen in most microphones? Or is bonding electronic and MEMS wafers together a better compromise? The answer may depend on the level of complexity,” Gilleo says. “While the somewhat simple electronics for accelerometers may be somewhat easy to add to the MEMS wafer, more complex electronics for lab-on-chip or analyzer-on-chip might perform best with two separate wafers. And as MEMS continue to gain in complexity, we may see the use of non-silicon for the MEMS wafer, the electronics, or both. This situation could drive wafer-level electronic/mechanical assembly, or multichip packages. And last, but not least, there’s the intellectual property (IP) issue. There have already been some MEMS packaging lawsuits, but expect many more. The industry, now forewarned, is more cautious about patent infringement.”

Will 3-D WLP MEMS technologies and processes prove beneficial to the IC industry?

Again, opinions vary widely on this subject—ranging from “no” to “the field is wide open.”

Kuisma says, no, because MEMS-specific vias are not cost-effective for IC vias. “MEMS devices will try to reuse everything that goes mainstream for the 3-D WLP of IC devices,” he adds.

Robert believes that memory (die stacking) and image sensors for the consumer segment are two applications where 3-D WLP MEMS technology can be used. “With respect to memory, this will probably be the market that will drive cost reduction to the industry, due to the very high potential volume involved. Dalsa has no plans today to participate in these markets, though,” he says.

And Gilleo suggests the field is still wide open for many technologies. “WLP is still mostly ‘lab,’ not ‘fab.’ But assuming that 3-D sculpting, TSV, and wafer bonding are key, the good news is that the technology and equipment needed to make it happen are ready,” he says. “And let’s not forget the very bright technologists who have moved into the field.”

Long-term vision for 3-D WLP MEMS

In terms of the outlook for 3-D WLP MEMS through 2015, Yole is forecasting a greater than 50% CAGR increase in demand for devices such as MEMS μ-probes, cooling chips, MEMS inkjets, MEMS microfluidics, MEMS IR μ-bolometers, MEMS resonators, MEMS RF switches, MEMS pressure sensors, MEMS micromirrors, MEMS accelerometers, MEMS gyroscopes, and MEMS Si-microphones.

“All the inertial sensors, pressure sensors, frequency sources, RF modules, and microphones in consumer electronics will be based on 3-D WLP of MEMS,” says Kuisma.

Dalsa expects 3-D WLP MEMS adoption to increase as an alternative to monolithic integration, thanks to the increased complexity of control electronics. However, this growth will be gated by the success of the industry to reduce TSV formation and filling costs. “Die-level co-packaging of the ASIC is the alternative approach and is the best solution when the die size between the MEMS and ASIC are significantly different,” says Robert. “The TSV technology used for 3-D WLP MEMS, however, can be used for MEMS devices only—without the limitation of the ASIC die size to reduce the MEMS die size and cost. Silicon interposers allowing 2-D integration are also another potential area for such MEMS technology. New materials and technologies are required to reduce the cost of the TSV.”

Gilleo says WLP MEMS are the only way to go, the ‘end game.’ “Once WLP is established, it will become the de facto standard for most, but not all, MEMS,” he notes. “WLP and MEMS are companion technologies. In my opinion, 3-D stacked electronics is borrowing heavily from MEMS already. MEMS form columns, openings, and microvias almost routinely. MEMS wafers have been capped at wafer level for many years and wafer bonding is also well established. Anyone in 3-D packaging should be looking at MEMS processes.”

Donald Robert is VP, of Sales & Marketing at DALSA’s Semiconductor Division located in Bromont, Quebec. In this role, he is responsible for the strategic and tactical activities related to the development of DALSA’s semiconductor products & foundry services. He holds a degree in electronics from Sherbrooke College and a degree in Business Management from the University of Sherbrooke and has over 27 years of industry experience. His areas of expertise include business development and semiconductor manufacturing.

Ken Gilleo, Ph.D., president of ET-Trends LLC. (Warwick, Rhode Island), has worked in the electronics industry for more than 30 years and in the MEMS field for nearly a decade, with a focus on packaging design and materials. He has written extensively on the topic, including a book “MEMS/MOEMS Packaging,” published by McGraw Hill. Much of his present activity is in the intellectual property area. Gilleo served as an expert witness in recent patent litigation involving MEMS packaging.

Heikki Kuisma, Ph.D., is director of MEMS concept development at VTI Technologies. He’s responsible for the advanced development and new product concepts. Kuisma has 28 years’ experience developing MEMS-based products.