Developing fan-out WLP

What’s behind the industry’s drive to develop fan-out WLP? There are several factors, according to Caroline Beelen-Hendrikx, NXP’s (www.nxp.com; Nijmegen, The Netherlands) director of strategy, operations backend innovation. “Thickness is one of the key drivers,” she says. “Thinner packages can be made with fan-out WLP in general, compared to regular BGAs. Fan-out WLP package thickness is between 0.3- and 0.5-mm, whereas most BGA are 0.65-mm thick or thicker. Since QFN/SON packages of 0.5-mm thickness are already on the market and thinner versions are in the works, fan-out WLP is less likely to be a replacement for those.”

Area is another driver. Fan-out WLP enables much smaller packages than BGAs or QFN/SONs, Beelen-Hendrikx says, because line width/space are smaller. However, when the second-level I/O or ball pitch is limited to 1.0- to 0.8-mm pitch by the capability of the customer’s board, she points out that it serves no benefit.

Risto Tuominen, chief technology officer at Imbera Corp. (www.imberacorp.com; Melbourne, Florida) also sees area as being one of the big issues driving fan-out WLP. “When area is an issue, in terms of fitting all the interconnects into a small space, fan-out becomes a solution. If the interconnects are going to be placed in the die area, then the pitch needs to decrease. We have one customer using 0.3-mm pitch, but most appear to be avoiding it as long as possible. Expanding to 0.4-mm pitch will result in a price increase.”

And cost is yet another significant driver. “Fan-out WLP cost depends on the number of redistribution layers, the size of the reconfigured wafer and, of course, on the package size. Even with one RDL layer and 12-inch reconfigured wafers, fan-out WLP is more expensive compared to QFN/SON of the same body size,” explains Beelen-Hendrikx. “When comparing fan-out WLP cost with the same-size wire bond BGA packages, fan-out WLP is at the same price level as small-size thin BGAs. Perhaps in a single case it would be cheaper. If you compare it to big wire-bond BGAs, fan-out WLP is certainly more expensive. There might be a cost benefit if you compare it to flip chip BGAs, which use more expensive boards than wire-bond BGAs.”

Brett Dunlap, director of advanced product development at Amkor (www.amkor.com; Chandler, Ariz.) sees cost as being the biggest driver at the moment. “The primary driver for fan-out WLP or wafer-level fan-out WLFO is cost reduction vs. current FBGA (laminate-based CSPs),” he says. “For FBGA, cost is driven by substrate technology. Specifically, increased laminate substrate routing density, which is determined by the IC’s I/O, power and ground interconnect density, and the requirement for small/thin package footprints. However, not all standard wirebond or flip chip IC design pad placement rules may achieve cost reduction in WLFO. Redistribution routing capability must be considered during I/O floor planning to achieve cost objectives.”

“Demand for WLP is being driven by shrinkage in size and height, a simplified supply chain, and a lower overall cost by using the infrastructure of a batch process,” notes Seung Wook Yoon, deputy director of technology marketing at STATS ChipPAC (www.statschippac.com; Singapore).

“There are some restrictions in possible applications for fan-in WLPs, since global chip trends tend toward smaller chip areas with an increasing number of interconnects,” says Yoon. “The shrinkage of the pitches and pads at the chip/package interface is happening much faster than the shrinkage at the package/board. This interconnection gap requires fan-out packaging, where the package size is larger than the chip size to provide a sufficient area to accommodate the second-level interconnects. Fan-out WLP has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology.”

Fan-out WLP applications

Fan-out WLP will likely be used as an alternative to thin BGA of low to medium pincount in highly miniaturized mobile equipment, says Beelen-Hendrikx, because it offers a smaller and thinner package.

Targeted devices include baseband (DSP), applications processor, power management, RF transceiver for wireless mobile or digital consumer product applications, where the I/O counts are up around 750, according to Yoon.

Applications will vary, believes Dunlap, who points out that cellphones are one area originally noted by the pioneers in WLFO technology. “No insurmountable barriers are apparent at this time. However, infrastructure for reconstituted wafers is immature,” he adds. “I expect the general market timing for first product to be the end of 2009 or early 2010.”

Some potential issues with fan-out WLP are board-level reliability for bigger devices (failure in temperature-cycle tests), and also yield issues, explains Beelen-Hendrikx. “Die shift during molding and mold curing is one of the major processing hurdles. Another critical point is the selection of the redistribution dielectric. As the reconfigured wafer needs to withstand the redistribution process, standard WLP dielectrics cannot be used,” she adds.

Tuominen says that he doesn’t see too many technical challenges remaining for fan-out WLP. “We’ve already done lots of these products and know how to do it and optimize it,” he says.

Fan-out WLP vs. embedded die in PCBs

Embedded die may compete with fan-out WLP in some applications, however, this will occur once the industry achieves a near-perfect (>99%) process yield for high I/O active die, according to Yoon. “Today’s progress in embedded die infrastructure suggests that it can be used only in low-end products, unless a technology breakthrough occurs. Area utilization is more attractive in embedded die technology, but for fine pitch, fine metal line applications, fan-out WLP provides better control and quality. Embedded die technology will be a solution for module-level packaging, while fan-out WLP is well suited for component-level packaging,” he says. In the future, Yoon expects fan-out WLP will expand its boundary to 3-D IC or 3-D SiP applications with vertical interconnection.

Beelen-Hendrikx believes fan-out WLP and embedding both offer packaging solutions for single-die packages and modules (multi-die). “A big plus for substrate-based packages and modules is that technology for TSVs is already available, and board-level reliability is probably better because materials used in the package and the substrate are more identical,” she notes. “An advantage for fan-out WLP is that smaller-die pitches can be handled because the line width/space is somewhat smaller (however, this is only true when there are no issues with die shift) and the dies don’t require bumping.”

Another advantage, Beelen-Hendrikx says, is that packaging is being done by packaging companies now. “In the case of substrate embedding, packaging must be done by substrate suppliers. This will change the supply chain. It remains unclear which technology will dominate. Probably both will be used, with a bigger share going to the cheaper solution. Companies that desire an in-house solution will prefer fan-out WLP. However, for bigger packages, they might need substrate embedding to guarantee board-level reliability.”

Fan-out WLP supply chain/partnerships

One of the inherent benefits of wafer-level packaging is a simplified supply and value chain. “With a majority of the process steps being performed at the wafer level, WLP uses the wafer fab supply chain already in place,” says Yoon. “Fan-out WLP doesn’t need any interposer, substrate, or leadframe for packaging, so the technology can be handled more independently by an assembly house or SATS with services such as design, fabrication, quality control, etc.”

In principle, a fan-out WLP is a WLP realized on a reconfigured molded wafer. In addition to the WLP processes such as redistribution and bumping, reconfigured wafers must be prepared. This requires wafer thinning and dicing, die placement and compression molding processes. “Any packaging company with experience in WLP and BGA/PoP packages is in a good position to develop fan-out WLP capability,” says Beelen-Hendrikx. “Because companies require second sourcing and standardization, licensing is a good way to build up capacity at several sources.”

Dunlap believes supply chain development and partnerships may be a benefit for initial applications to ensure target ICs are designed for WLFO to achieve cost targets as well as to ensure multiple sources of supply exist with sufficient demand for the supply chain to achieve return on investment and the critical scale necessary for WLFO to meet cost objectives. “Once the WLFO applications and infrastructure has matured, partnerships may be less critical for other IC makers to adopt the technology,” he says.

Next steps in the evolution of fan-out WLP

The next steps in the evolution of fan-out WLP will likely be through-mold vias to enable PoP, Beelen-Hendrikx believes, because PoPs made from fan-out WLP are considerably thinner. We should also look for integration of thin-film passives in the redistribution layers, such as inductors or capacitors, she says. And the use of multi-die fan-out WLP for side-by-side die configurations will be limited because of board-level reliability.

Yoon expects to see 3-D embedded wafer-level ball grid array (eWLB) technology enable 3-D IC and 3-D SiP packaging with vertical interconnection. “3-D eWLB can be implemented with TSV applications, as well as discrete component embedding. Further exploration of large-area utilization in eWLB technology has the potential to reduce assembly cost,” he says. “STATS ChipPAC is planning to integrate separately developed infrastructures for integrated passives on silicon, embedded, multichip, 3-D integration in SiP, PoP, and fan-in PoP.”

Caroline Beelen-Hendrikx, director of strategy, operations backend innovation at NXP, is responsible for the semiconductor packaging roadmap. She has 18 years’ experience in electronics packaging and assembly at Philips and NXP as a process engineer and development manager.





Brett Dunlap, director of advanced product development at Amkor, is responsible for wafer-level fan-out and integrated passive technologies. Prior to Amkor, Dunlap worked at STATS ChipPAC, where he was responsible for development of their integrated passive technology and later held the wafer-level business manager position. Before joining the OSAT world, Dunlap was employed at Medtronic Inc. for more than nine years. Dunlap received a B.S. in chemical engineering from the University of Tucson.

Risto Tuominen, chief technology officer at Imbera Corp., is responsible for technology licensing, technology roadmaps, R&D, development, adoption, and ramp-up to high volume. He graduated with a MS from Helsinki University of Technology. His major was Electronics Production Technology, and for his thesis he developed the first integrated module board technology generation. He later launched Imbera and served as CEO.

Seung Wook Yoon, Ph.D., MBA, deputy director of technology marketing at STATS ChipPAC, is in charge of technology marketing of next-generation integration technology, including TSVs, embedded packaging, integrated passive device, and 3-D IC packaging. Prior to joining STATS ChipPAC, he was deputy lab director of the Microsystem, Module, and Components Lab at the Institute of Microelectronics in Singapore. Yoon received a Ph.D. in materials science and engineering in 1998 from KAIST in Korea. He also holds an MBA from Nanyang Business School in Singapore. He has authored more than 80 journal and conference papers, and holds several US patents on microelectronic materials and electronic packaging.