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Dec 11th, 2013
Polymer via-filling to improve reliability of 3D-IC / TSV packaging
The successful progression of three-dimensional (3-D) integration on multi-level chip designs has enabled the evolution of smaller, faster and smarter devices.
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Consumer demand for multifunctional electronic gadgets with reduced form factor has therefore greatly stimulated 3-D integration for the past several years. A key driver for 3-D device integrat ions chemes has been the realization of through-chip communication between multiple vertically stacked layers using through-silicon via (TSV) technology. The fabrication of TSVs, however, is not trivial and involves a series of processes mainly concerning wafer thinning, deep reactive ion etching, dielectric deposition, and electroplating of the actual through-via metal interconnection. Currently, mostly sol id Copper (Cu) via structures are employed in TSV interconnects.

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