It’s no secret that 3-D ICs will require new thermal management materials solutions, and preferably ones that can leverage existing infrastructures to ensure they’re easily adoptable.

One of the primary motivating factors behind using through-silicon vias (TSVs) and 3-D chip stacking technologies is the desire to reduce electrical latency. As line size is reduced, the capacitive resistance increases, placing a “drag” on the electrical signals that are transported around the chip. At a certain size, speed improvements stop. The solution? Shorten the signals transmitted across the die by dicing up the die, and then go vertical.

With 3-D chip stacking, removing heat from the highest heat-generating chip and then essentially pushing it through all the lower heat-generating chips and trying to take it out the backside of the chip isn’t very efficient. And putting thermal vias into each of the die to pass the heat through a stack would involve placing so many thermal vias that it wouldn’t be feasible to route within the die. Completely passive approaches are unlikely to succeed for 3-D thermal management once the chip reaches a certain level of heat generation.

As an alternative cooling option, Nextreme Thermal Solutions Inc. (Durham, NC; www.nextreme.com) is proposing methods to remove heat from the front side of the die. “Nextreme is removing the heat laterally through an interposer, so you can imagine some of the chips would be below an interposer, and that the interposer would be at a fixed temperature and you’d be removing the heat from the side,” explains Paul A. Magill, vice president of marketing and business development at Nextreme. “And you’d mount the rest of the chips on top, the least heat-generating chips, and could use a classical means such as fan and heat sink for heat removal.”

Thermally active copper pillar bumps with a thin-film thermoelectrical material embedded inside them, developed by Nextreme, are capable of rapidly cooling one side relative to another when a current is run through them (Fig. 2). They were engineered to address thermal and power constraints in electronics, according to Magill, and are scalable and cost efficient. In a 3-D stack, multiple bumps may be placed in various layers, and it’s also possible to integrate a passive layer that is intended solely for cooling purposes. These bumps can be used for active-side, back-side, and lateral cooling.