The semiconductor industry has historically invested exclusively in chip design while the dicing operation has always been approached as a must do, non-value add step.
Truth is, it exclusively allows separating each die and as a result, the material in the streets is lost to dust.
Blade and more recently laser cut have been developed, as a sequential process where die has to be placed on an orthogonal pattern due to the linear cut trajectory. This commands square or rectangle die with sharp corners.
The push for end product performances (faster, greener, thinner) has resulted in the emergence of More than Moore trends such as 3D and 2.5D packaging, system in package, and heterogeneous die integration, and evolution of packaging from wire bond to bumped wafers for most advanced nodes.
All these innovations are putting more constraints on designers to cope with reliability, energy consumption, density of integration of complex systems and thinner and thinner substrates.
In this webcast, we will illustrate how Plasma dicing can not only solve inherent die strength, chipping, lateral damage issues resulting from current dicing techniques but also how this process step can be a value add operation by
- Generating unique gain in active silicon area resulting in contributing to increase good die per wafer up to >30%
- Reducing the need for wafer starts and upstream equipment investments
- Enabling non-orthogonal and optimal die patterns for increased DPW, improved packaging density, and optimal die performance.
- Reducing stress in package
- Improving device performances for various products such as Power, LED, Memory, Logic, MEMS or CMOS Image Sensors, especially in relation to current trends in wafer thinning.
- Resulting in fast ROI and low CoO compared to existing dicing techniques.
Thierry Lazerand, Director of Technical Marketing, Plasma-Therm
Thierry is leading the development and market introduction of the plasma dicing technology. He received his Master in Material Sciences from University of Limoges and MBA from University of Nantes in France. His experience in the semiconductor industry spans over 30 years with various lead roles in front end device manufacturing. His assignments cover fab device engineering, European manager for field applications for capital equipment, technical marketing and business development related to cleaning, thermal and plasma deposition, etch and atomic layer deposition. Mr. Lazerand co-authored several publications in these fields and is the co-founder of Sunsonix, a start-up delivering bio-degradable chemistries for PV Solar and emerging green markets.
Gordon Grivna, Staff Scientist, ON Semiconductor
He has a primary focus on new product development and integration. He received B.S. degrees in Chemical and Metallurgical Engineering from the Univ. of Minn., USA in 1981. Since 1981 he has worked in multiple aspects of Semiconductor process development and integration where he has authored several papers and been issued over 80 process and design patents.
Pars Mukish, Activity Leader, LED & OLED, Yole Développement
Pars Mukish holds a master’s degree in Materials Science & Polymers and a master’s degree in Innovation & Technology Management (EM Lyon – France). He works at Yole Développement as Activity Leader - in the fields of LED, Lighting Technologies, Compound Semiconductors and OLEDs - to carry out technical, economic and marketing analysis. Previously, he has worked as Marketing & Techno-Economic Analyst at the CEA (French Research Center).
Moderator: Jérôme Azémar, Yole Développement