> Laurence Pujol, R&D Manager of BEAMIND

Laurence Pujol is the R&D Manager of Beamind. She has 20 years of experience in industrial development of mecatronics and opto-electonics systems. She graduated from INSA (Lyon) in Materials science. She has lead many projects developing sub-systems for satellites or for the automotive industry including high precision optical metrology, integrated optics and opto-mecanical sensors, mainly in the field of dimensional measurement. Before joining Beamind, she held the position of CTO and COO of SAGESCSO, a SME manufacturing miniature interferometers for industrial applications. She joined Beamind in May 2006.

What are the motivations to adopt the LDT technology? Which kind of test procedures does this technology address?

The LDT technology is dedicated to open and short failure detection. It is basically a capacitance measurement of the tested trace. Thanks to photo-electrical effect, electrons can be injected in a trace or removed from it, changing thereby its electrostatic potential. By controlling the voltage of the trace and measuring the transferred charge, the system derives the capacitance of the trace under test.

The LDT is a disruptive technology for electrical testing in many points. The measurement is entirely contact less: UV laser energy is optimized to perform electron extraction without ablation, leaving no mark on the test pad. Laser can focus on very small spots, leading to a very good ability to test very fine pitch patterns. UV laser beam size is today smaller than 60μm and could be reduced further, down to a few microns. Laser movements are controlled by scanning mirrors that are 10 times faster than the mechanical probes used in the flying prober technology. The testing speed and test productivity can then be increased up to 150 TPS (Test Point per Second). The position of the laser beam is fully programmable; no fixtures are required as in the beds of nails testing technology. That flexibility greatly reduces the total cost of ownership and line setup time and is presently very useful for testing small to medium series.

 

Can you tell us more about the technical capabilities of the LDT equipment when applied for testing 3D TSV interconnects?

The benefit of this contact less technology exceeds the field of PCB. Due to LDT technological advantages, it can also be very useful in the silicon industry. As an example among many other applications : the capacitance measurement applied to fine pitch can be used to test TSV (Through Silicon Vias) and redistribution interconnection layers. The use of “optical probe” enables to test very small patterns, down to few microns, where spring probes have very poor performances and can ultimately mechanically damage the device.

LTD is a clean technology that doesn’t generate neither scraps on silicon wafers nor contamination. Moreover, vacuum level under which the LDT system operates is adequately compatible with the wafer process cycle. Foreseeing the evolution of 3D stacking of ICs components and challenges expected to test complex packages, LDT technology will become an inevitable key technology in advanced IC manufacturing, due to its capability of addressing both organic and silicon substrates and a wide range of pattern sizes.

 

In which markets do the LDT technology gain most traction at the moment?

The equipment currently available is dedicated to PCB substrates, mainly FC-BGA and FC-CSP (strips). For these markets we have already performed samplings to compare the LDT performance against standard probers: reliability in shorts and opens detection, flexibility (measuring several pad types and pitches) and productivity. The system for testing small and medium series is currently available and under assessment by IC substrate makers. For 3D-IC packages, the difficulty is to foresee which technology is going to enter first the high volume manufacturing phase. In order to have an overview ofthe interconnection testing needs, BEAMIND is involved in two research and development programs. One is a French program involving a French IC manufacturer, where BEAMIND will test medium density TSV in silicon.

The second one is a European program, dedicated to the validation of technological solutions for the fabrication of high value-added heterogeneous components and systems. It gathers the majority of the European actors of the domain: material providers, laboratories, research centers and manufacturers of equipment, components and systems. The tests of assemblies used in these different “More than Moore” systems have been identified by the consortium as a key point. This program should allow us to set technical specifications for test systems dedicated to 3D IC packages.

 

Could you share with us your vision about how optical contact-less based test technologies are poised to impact the semiconductor & circuit assembly industries in the future?

Manufacturing of complex System-in-Package including devices using heterogeneous technologies working together requires a convergence in interconnection definition. Pad sizes and pitches used in IC and interposers need to merge in order to make the interconnection possible. This convergence will lead, for density improvement reasons, to a dramatic decrease in pitch and size of interconnection components; bumps pads, Through Silicon Vias, etc… This decrease will become difficult to test with standard mechanical probe testers. Moreover, lifetime of these complex systems shortens as end products change very quickly. Test equipments will have to follow this evolution and provide the manufacturers with fine pitch capability, flexibility and increased productivity.

The IC package substrate industry already adopted the Laser drilling and Laser Direct Imaging technologies. Use of optical systems for the PCB industry led to improvement of fine pitch designs manufacturing and their use is unavoidably rising for organic substrates and interposers production. The laser Direct Testing technology utilizes all known laser properties for electrical test, is suitable for the newest generation of high density PCB substrates and will slowly be introduced into the 3D staked IC packaging market place.