> Giles Humpston & Bents Kidron, from Tessera

Giles Humpston, Ph.D., serves as Director, Research and Development of Tessera. Dr. Humpston has spent his professional career working in the field of semiconductor packaging, initially for military applications and, more recently, for high volume consumer products. He is a metallurgist by profession and has a doctorate in alloy phase equilibria. Humpston is a cited inventor on more than 75 patents and has co-authored several text books on metallic joining processes. His work and technical publications have been recognized by five international awards. Humpston’s current interests are packaging of solid state camera modules and product miniaturization through wafer level technologies.

Bents Kidron assumes ownership for all marketing and business development for all wafer level technologies in Tessera, including WLP (TSV), WLO (Wafer Level Optics), WLC (Wafer Level Camera).

Could you define what a wafer level camera is?

Wafer level camera is “wafer level manufacture of all parts of a solid state camera that are then combined at the wafer level”. The final step of manufacture is wafer dicing, which frees complete and individual camera modules. Recently the technical issues to make wafer level cameras have all been solved and product announcements appeared in 2007. However these first generation wafer level cameras are not manufactured according to the methodology suggested by the definition above. This is because it is perceived as uneconomic to do so. The issue is that the optical area of an imager die is very much smaller than the die area because of the other electronics each chip contains. The result is a mismatch in population between the lens wafers and the semiconductor wafers; a 200m diameter lens wafer being able to accommodate about 4 times as many lenses as an imager wafer containing VGA resolution die. There is also the issue of compound yield when mating a stack of optical components fabricated at the wafer level with a wafer containing imager die. In both cases the number of good optical die is less than the total number of die.

Consequently it is economically more favourable to make the optical train at the wafer level, dice it into individual optical stacks then conduct die-to-wafer assembly to build camera modules. Dicing the populated semiconductor wafer yields completed camera modules, an example of which is shown in Figure 1. A slightly less rigorous definition of a wafer level camera that takes this reality into account is, “wafer level manufacture of all parts of a solid state camera that are combined while at least one part is at the wafer level”.

 

What are the advantages of WLC approach?

The attractive attributes for wafer level cameras can be listed as follows:
• Compact form factor. A VGA resolution wafer level camera can fit comfortably in a cube less than 2mm on a side and mega pixel cameras are insignificantly larger.
• Low cost. Mechanical integration of a camera module in a cell phone costs several dollars. Reflowable wafer level cameras can be integrated at the same time as all the other surface mount components, making the sub-$1 VGA camera module a distinct possibility.
• Improved reliability. Traditional camera modules are connected to the main PCB by a flexible circuit and miniature connector. Failure of these components is the primary cause of field returns of cell phones exhibiting camera faults.
• Repeatable performance. Because all the parts of a wafer level camera are fabricated in parallel, they are virtually identical. The piece part variability is therefore reduced to a wafer basis and with many thousands of parts on a single wafer the distribution over the volume of the production run is much tighter than for discrete assembly.
• Superior performance. Wafer level optics can be fabricated with lens profiles unachievable by other means. This means the lens designer has many more degrees of freedom to achieve the desired image quality (see Figure 2). Combined, these benefits provided impetus to the endeavour necessary to convert the long held dream of the reflowable wafer level camera into a commercial reality. At the outset three barriers to widespread adoption of wafer level cameras were identified. They are:
- Technology
- Supply chain
- Cost and competition

 

What are the main technical challenges to make WLC today? Can you comment where the pain points are?

The principal technical challenges to making wafer level cameras are how to manufacture suitable lenses, combine these with other essential parts like apertures and filters, and then align and assemble these in a manner that yields an integrated optical component.

Wafer level lenses are all made by replication processes. While these are well known and understood and suitable equipment is available commercially, there is a major issue in that traditional optical polymers are wholly inadequate for wafer level camera optics. Key attributes are optical performance, mouldability and compatibility with the thermal excursion of the lead-free solder reflow cycle, typically 265°C for 2 minutes, x3 cycles. Wafer level cameras currently suffer from the problem that the volume of optical polymer required is insufficient for the chemical companies to justify investing in the development of new formulations. Consequently the companies that have developed successful wafer level optics technology have paid for the polymer development privately and all details about their chemistry properties and useage remain closely guarded trade secrets. This is clearly demonstrated by the lens slopes and sags. The optical design of wafer level cameras is limited by the achievable lens sag, which for commercial optical polymers and mastering techniques is around 200um [SSEC 2009]. Higher values allow a camera module to maintain the same form factor but grow progressively in resolution. More than one company is demonstrating lenses with >500um sag and >50 degree slopes on pre-production samples for >3MP reflowable wafer level cameras.

Early wafer level cameras were built to mirror discrete counterparts on a piece by piece basis. Now the optical trains are extremely complex, exhibiting double-sided lenses where each surface can be a different material and size with different profiles and coatings . To achieve this degree of sophistication required a number of technical problems to be solved, including wafer bow after replication, lens figure error and lens dicing (the two key issues here being to ensuring the polymer lenses have adequate adhesion to the substrate and the avoiding contamination of the lens surface). As with the lens materials, there is little published information on the solutions, but that they have been solved is evidenced by product availability from more than one source at pricing that is aggressively competitive with discrete manufacturing and assembly.

Similarly, the technology for mastering of lenses for wafer level cameras has advanced to the point where can be done directly for a fully populated 200mm wafer to the slope and sag specification listed above. Previously masters had to be built using step-and-repeat or stitching methods, both of which give rise to alignment errors that are difficult to control. Clearly, direct mastering is a far superior approach. Although the equipment to make large masters is commercially available, it is sold without the know-how to achieve the placement accuracy, profile deviation and surface roughness necessary for camera lenses. This information is hard won and closely guarded by the companies that specialise in making lens masters.

The optical train of a camera module consists of more than just lenses. To function correctly it must also contain, apertures, baffles, pupils and anti-reflection coatings to name a few. All of these components can be realised with semiconductor processing techniques at the wafer level.

Assembly of optical components in a stack requires precise alignment in plane, rotation and tilt. The alignment accuracy is limited to the equipment capability, which is barely adequate for optical applications. The requirement is for front-to-back alignment of lenses fabricated on each side of a single substrate and wafer-to-wafer alignment to fabricate the camera module at the wafer level. Two complementary approaches are used to solve this problem. The first is good optics design, which takes into account the limitations of the equipment. For example good practice is to set the focus depth between the lens stack and imager to larger than the equipment 3 sigma metric. However this imposes constraints on other aspects of the optical performance of the design, which is not always desirable. Accordingly, great attention is being paid to techniques for getting the best possible performance from the assembly equipment. One exhibiting great promise is innovation in optical alignment marks, which are, of course, easily integrated with a wafer of optical elements. Another approach is active alignment. Commercial equipment capable of active alignment is too slow and too expensive to be used for assembly of wafer level cameras. The contract assembly companies have invested heavily in proprietary active alignment tools to the extent that a complete lens stack can be built and integrated with an imager using active alignment for each level of assembly including full-field measurement of MTF, taking only seconds per part.

 

WLC manufacturing involves new technologies to be mastered. How the “traditional” camera module supply chain will be impacted by the introduction of WLC?

The camera module supply chain is currently built around the premise of component-to-component assembly. Lenses and other optical components are obtained as discrete items, and assembled in to a barrel. Meanwhile, the imager die is attached and interconnected to a substrate using chip-on-board processes. A housing that goes over the die is attached to the substrate and the barrel screwed into the housing. Once the camera focus is correct the lens barrel is set in position.

However this is not the entire picture. Camera modules manufactured from discrete parts are not compatible with solder reflow assembly. Consequently, the camera module has to be mounted on a flexible circuit that has an expensive connector at one end. Then, in yet another unique and serial process the camera module has to be aligned, attached and integrated into the cell phone housing or digital still camera body and the connector mated with its socket on the main PCB. The net result is that it can costs the cell phone manufacturer upto $4 to incorporate a $2 camera module (see Figure 3). The value proposition of the wafer level camera is that not only is the camera module cheaper per se, but it is reflow compatible so can be mounted on the main PCB at the same time as all the other surface mount components. In other words, at zero incremental cost to the cell phone manufacturer.

One of the difficulties of any disruptive technology is that it is difficult to adapt the existing supply chain to start production, no matter how compelling the economic case. This is true in the case of reflowable wafer level cameras and thus far the majority of companies servicing this product are new entrants to the field of camera modules. New companies can afford to enter this space as they have no legacy contracts to fulfil, or equipment to write-off and the first adopters always get the highest value, which is sufficient to offset their investment costs. The emergence of wafer level cameras will either force the remainder of the supply chain to adopt to this technology or the new entrants simply grow until the volume demand is satisfied.

In evaluating the impact wafer level cameras will have on the supply chain it is important to recognise that this innovation merely addresses cost and form factor. Wafer level cameras do not yet have any significant impact on performance. Performance improvements are likely to follow from the incorporation of technologies like Smart Optics, which give rise to features like continuous depth of field, ultra fast lenses and optical zoom with no moving parts. These developments can all be easily integrated into wafer level camera modules, but are either difficult or impossible to integrate with discrete assembly techniques. This will eventually lead to camera modules built using discrete assembly in the unhappy position of being physically larger, costing more and offering inferior performance. Based on this understanding, it is perhaps not surprising that market analysts predict that wafer level cameras will take more than 30% market share by 2012 [TSR, 2008].

 

What are the benefits for camera module manufacturers to invest into new equipment and facilities for WLC?

Although the raw cost benefits of wafer level camera technology may appear compelling, to enter this market still requires substantial investment in new equipment and facilities. Once this investment is made it provides the camera module manufacturer with great flexibility in terms of the product range and mix they can offer. This arises because the much of the equipment is common, irrespective of whether the manufacturing company wants to pursue a strategy of wafer level packaging of imagers, manufacturing wafer level optical assemblies or building complete camera modules. A combined product line maximises the return from the investment as the capacity of most equipment exceeds the requirements of relatively high volume manufacture, enabling multiple product types to be run simultaneously. Even better is that the same equipment set is used for camera modules ranging from QCIF to multi-mega pixel resolution so no additional investment will be required until the transition to 300mm diameter wafers occurs, towards which there are not yet any obvious moves.

The current supply chain for camera modules fabricated from discrete parts is long with many entities involved, each adding margin. Wafer level camera assembly is done as a one-stop endeavour making it simultaneously a more profitable venture for the camera module manufacturer and reduced cost component for the system integrator. It is therefore unsurprising that the production of reflowable camera modules has ballooned from less than 1,000 per year in 2006 to 10,000 per month in 2008 [TSR 2008].

 

Do WLC necessitate specific packaging, in particular with Through Silicon Vias?

As might be expected, there are several competing wafer level optics technologies commercially available. To manufacture a camera module entails not just lens technology, but also the ability to package the imager at the wafer level and provide the package with a ball grid array interface. Connection of the bond pads on the die to the package lands requires a through silicon via (TSV) technology.

The problem with TSVs is that they are bedevilled by high cost and questionable reliability. Several companies now offer TSV technology for image sensors, although only one meets the base cost necessary to achieve the sub-$1 VGA camera module and has published reliability data demonstrating the package will not only surpass by a wide margin the cell phone specification for reliability but also the more arduous automotive specification as well [IEEE 2008].

 

To conclude, what is your future vision for WLC?

Wafer level cameras are manufactured by combining, parts that are fabricated and assembled at the wafer level. Their value proposition is based on substantial savings in cost, much smaller form factor and a manufacturing line that is product agnostic. Realising this value entailed solving many technical issues. Wafer level camera technology is still in its infancy but so compelling are the benefits that fully reflow compatible, wafer-level cameras with VGA resolution have been developed, designed in product and manufacturing volume is ramping fast. Multi megapixel variants are not far behind. It is forecast that within 4 years reflowable wafer level cameras will account for more than 30% of the 2bn camera modules manufactured annually.

References
SSEC 2009 Semiconductor International, 6th February 2009, “Inside wafer-level Cameras”

TSR 2008 Techo Systems Research Company Ltd, December 2008 Researching Report, “Market breakdown of camera phone – 1st half 2008 & 2nd half 2008 forecast”

IEEE 2008 G Humpston, “Novel and low cost through silicon via solution for wafer scale packaging of image sensors”, Proceedings IEEE Electrical Design of Advanced Packaging and Systems Symposium, Seoul, 10-12 December, 2008