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Jan 30th, 2013
Impact of TSV induced mechanical stress on FinFET devices
While the industry is finally introducing 2.5/3D products at 22nm node another IC technical breakthrough is happening at the same time, namely the use of “finet” based devices. Use of these devices has been announced by Intel, TSMC, GlobalFoundry etc.
At the recent IEEE IEDM meeting in Dec of 2012 Wei Guo and co-workers at IMEC reported on the impact of thermo-mechanically induced stresses by copper TSVs, on fully depleted Bulk FinFET devices. i-Micronews thought this was worth… A Closer Look.
3D stacking and fully depleted devices have both emerged as a path to achieve the requirements of mobile applications at 20nm and beyond. The impact of TSV proximity on this advanced CMOS remains a major concern . The difference in thermal expansion between the TSV metal and the Si substrate causes mechanical stresses in the silicon that may affect carrier mobility in the electronic devices impacting their performance. The impact of TSV proximity on planar CMOS devices has been reported previously and thermo-mechanical models have been developed to understand these effects [1, 2].In this work IMEC reports for the first time the impact of 3D Cu-TSV integration on bulk FinFETs, in a non-planar fully-depleted device.
The FinFET CMOS test vehicle was fabricated on IMECs 300 mm pilot process line. The HKMG FinFET technology consists of Si fins with a 40nm fin height, 20nm fin width and different fin lengths. The advanced gate stack is based on a gate-first high-k integration with HfO2 insulator and TiN metal gate. The “via-middle” Cu TSV is implemented before the first Cu-damascene metal layer processing. The TSV diameter is 5μm and depth is 50 μm (aspect ratio 1:10). The minimum TSV pitch is 10 μm. A 200nm oxide liner electrically isolates the TSV and a Ta/Cu barrier/seed layer is deposited by PVD. Electroplating process is used to fill the TSVs. A high temperature anneal is applied to stabilize the stress condition of the Cu in the TSV. After processing (Cu anneal to mitigate Cu-pumping), the Cu in the TSV is in a tensile stress condition that is in the 400-600 MPa range at 300K.
The stress response of FinFET differs significantly from planar devices, due to the non-planar channel of the FinFETs and very narrow fin structure embedded in the oxide.
Average current variation for planar devices as a function of their
These proximity effects were further analyzed on a analog circuit consisting of a n- and p-type Digital Analog Converter (DAC) circuit including an array of current sources. Each analog FinFET device has Lg= 6μm and 40 fins with current flow in the horizontal direction. The TSV-induced p-FinFET Idsat variation is up to 2.5%, and for n-FinFET it is 2.5%, which is less than p-planar DAC array previously measured at around 4.5% variation .To meet 10-bit accuracy requirement a maximal change of 0.5% is acceptable, resulting in a keep-out-zone, KOX, of 13μm.
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