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Feb 20th, 2013
eSilicon enables 2.5/3D architecture and the supply chain
One of the issues in bringing 2.5/3D IC products to market certainly has to be maneuvering the infant evolving infrastructure. i-Micronews has heard that several IC houses have been working with eSilicon to bring their 2.5/3D products to market. i-Micronews thought this was worth: A Closer Look.
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We were recently able to talk to Javier DeLaCruz of eSilicon about the eSilicon MoZAIC™ program.

Yole Développement: How about a little personal background first. Where were you before eSilicon and what is your role currently at eSilicon?
Javier DeLaCruz: I started my career at M/A-COM primarily working on analog package design and manufacturing.  After that I was at STATS (now STATS-ChipPAC) as a technical program manager working to bring new projects to production throughout the eastern U.S. and Europe.  I then spent some time at Multilink focused on high-speed optical networking devices in the 10Gbps and 40Gbps space.  For over 10 years now, I’ve been at eSilicon where I am now senior director of manufacturing technology which encompasses die-package co-design as well as the associated signal and power integrity domains.  More recently I’ve led the team in the development of our MoZAIC 2.5D/3D program. 

YD: May we have a little intro on eSilicon for those readers who are not familiar with your company?
eSilicon was founded in 2000. It is a semiconductor design and manufacturing services provider managing the design and operational aspects of producing custom silicon for its customers. eSilicon leverages the efficiencies of producing many devices, utilizing several partners, more cost effectively than its customers could if they tried to do this themselves. The knowledge we gain from over 20 tapeouts per year ensures a higher likelihood of timely tapeouts and functional first silicon.
eSilicon is a leader in delivering functional first silicon in emerging nodes. To that end, eSilicon has a strong focus on package, signal and power integrity, which cannot be performed in isolation. From eSilicon’s early days, package co-design with silicon and system awareness has been key.
Another key element of eSilicon’s approach is flexibility. Customers can choose to design the die themselves and have eSilicon design the package; have eSilicon take complete control of the entire design; have eSilicon complement a customer’s design resource with additional skillsets; or simply have eSilicon manage the production of a released product. eSilicon’s goal is the same as the customer’s: shipping cost-effective silicon. eSilicon’s expertise is the ability to get products to functional production, reliably and quickly. 
While eSilicon relies on partners to actually manufacture the ASIC devices, all of the human core competencies needed to design and produce these devices reside internally.

YD: We’ve heard you say that you are seeing a shift away from standard SoC technology. Can you expand on this for our readers?
:  There are several dynamics that are moving the industry away from the SoC philosophy that was so popular just a few short years ago. One of the significant factors is the cost per gate for CMOS nodes below 28nm is rising for the first time in the history of our industry. Another critical factor is the emergence of thru-silicon-via (TSV) technology as a viable package element. Other factors include the inability for memory density to keep up with processing demand and the limitations of copper interconnects for high-speed signal transmission. With these industry changes, several companies are shifting their crosshairs to technology enablers such as 2.5D and 3D integration, and eSilicon’s MoZAIC program is focused on enabling this transition.

YD: So introduce us to your MoZAIC program. What is it all about?
:  MoZAIC stands for “Modular Z-Axis IC.” Our MoZAIC program provides:
- Tile selection from a library (a tile is a die that is designed for 2.5D and 3D assemblies)
- Tile reuse over multiple projects
- Use of lower nodes only where required
- Only the base layer is customized and NRE is low because the base layer can be built in an older process
- Best of both worlds: access to leading-edge functions with trailing-edge NRE

eSilicon’s MoZAIC program

Our MoZAIC program deals with the complexities and solutions for integrating die from multiple suppliers in a 2.5/3D-IC. eSilicon can act as the central integrator, bringing together disparate supply chain partners and managing the complexities of the new model. .

With 2.5D and 3D architectures, there are new links in the supply chain, including:
• Interposer manufacturers
• Tile suppliers
• Third-party foundry services for partial wafer processing
In addition, existing links in the chain have become more complex:
• The ability to mix technologies and nodes opens the door for additional foundries for different components in the same 2.5D or 3D assembly.
• OSAT (outsourced assembly and test) can perform a more complex role and contribute more to the value chain as items such as memory stacks, optics, and MEMS devices can be integrated within the package. This poses an inventory challenge, a yield ownership challenge and a procurement challenge because OSATs are generally not keen to directly source these high-cost components.
• Test challenges are very significant because components within 2.5D and 3D assemblies may not be completely testable until the assembly is complete, which results in a higher monetary risk for each failed component. Novel approaches to mitigating these test and yield issues are required.
The MoZAIC program encompasses architecture tradeoffs for planning purposes that can be weighed very early in the planning phase to design a device that meets end-market needs.

 eSilicon’s role as integrator in the 2.5D/3D infrastructure

Yole: Can you discuss a little further the “tile” or chip sources?
We basically see three tile sources:

- eSilicon partners with common technology types that are used across multiple applications and customers
- eSilicon will build up its own library of tiles
- e.g., memory, FPGA, high-speed interfaces, etc.
- eSilicon ASIC solutions developed by/through eSilicon
- e.g., integration of a partner’s ASIC into a larger 3D-IC
- Third parties with application-specific solutions generally chosen by eSilicon’s customers
- e.g., ASIC, custom analog, high-speed PHY, etc.

YD: Are their issues with the die design that a novice might not appreciate?
Yes, the die design process is much more complex as different types of interfaces must be used between 2.5D and 3D tiles than would otherwise be needed. These interfaces are much lower power and higher density than conventional SerDes or DDR interfaces. There is little reason to use a SerDes or a higher-voltage interconnect to simply go from one die to another in the same package. The architecture of such devices is dramatically different as the die need to be designed with a different type of hierarchy in order to leverage different wafer nodes and technologies. There is an opportunity to dramatically drop the power of 2.5D and 3D devices if the architecture is planned correctly and the IP and tiles are available. These are issues on which eSilicon has been focused for years.

YD: Some “nay sayers” point to increased complexity as increased cost. What are eSilicon’s thoughts on this?
: While this is somewhat true, it has to be weighed against the simplified system-level integration. Most printed circuit boards (PCBs) in networking, storage and computing applications are very high-layer-count PCBs. These are usually used to gate the memory interface between a processor and the memory it accesses. If a 2.5D or 3D device has the memory already integrated into the package, then the PCB would no longer need nearly as many layers. In addition, with the memory included in the package at a higher bandwidth and capacity and lower power, the package interconnect count is reduced considerably. The memory interfaces that once dominated the ball assignments would be available for other functions or assigned as power supplies. The main interface remaining would be high-speed SerDes and eventually optical interconnects. Therefore, the area efficiency of 2.5D and 3D devices compared to traditional ASICs (including the area taken by the field of memory) would be vastly improved. Furthermore, the complexity of assembly on a given board (assuming similar functionality) would also be simpler. In our discussions with OEMs, none of them would actually keep the same functionality on a PCB. Instead, they would simply put more processing power on the same PCB, mainly due to the area savings of a 2.5D or 3D approach. They would still benefit from a lower PCB layer count.

YD: How do you see the role of the IP supplier evolving in the 2.5/3D world?
As the market shifts towards 2.5D and 3D integration, IP suppliers have a potential role change as usage of their IP becomes similar to a standalone piece of physical silicon. Hence, these companies can leverage their expertise to sell standard product instead of just IP. IP providers for such IPs as processors, SerDes, and various memory types are not generally experienced in die sales and the complexities therein—eSilicon is, and can facilitate that migration. We have already discussed, with various IP providers, leveraging our existing infrastructure to have eSilicon manage the sales of these IP tiles into various products. This is design and reuse methodology as these IPs would be available in a tile library meant for reuse across multiple projects.

YD: What is eSilicon’s perspective on the readiness of the infrastructure for the coming 2.5/3D revolution?
With higher levels of co-design required for these devices, several links in the chain are not correctly prepared for this increased interaction.

OSATs do not generally have the expertise in device architecture needed to effectively take advantage of the key benefits of MoZAIC-type devices. Alternatively, with the lack of industry standards in test interfaces, bump geometries, interposer types, interface patterns, etc., there are too many open variables to easily decide where to start planning.

eSilicon’s MoZAIC program has developed interface patterns that work in a variety of interposer technologies and have activity in place to qualify these at multiple OSATs. This data—along with integrated architecture planning, a future library of existing tiles, and a solution that can be reliably assembled—will enable our customers to cover the new complexities introduced with 2.5D and 3D architectures and allow them to focus on truly leveraging the benefits of 2.5D and 3D with their new devices.

YD: Thanks for your time Javier and best of luck in helping move the 2.5/3D infrastructure forward.



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