Through-wafer insulation has been used to develop technologies such as Sil-Via TSV and Zero-Crosstalk. TSI, or through-silicon insulation, is the processing of silicon wafers by MEMS techniques to create dielectrically isolated areas of the silicon.
Fig 1: SEM image of TSI DRIE etch through silicon.
By taking advantage of the high aspect ratio and vertical sidewall capabilities of deep reactive ion etching (DRIE), trenches can be formed in silicon which extend all the way through the silicon wafer (FIGURE 1).
The final wafer after TSI processing exhibits islands of single crystal silicon separated by high quality isolation. This structure is the basis of TSI, and forms the building block of many of Silex's offered technologies. TSI has been compared to either a dielectric isolation (DI) or silicon-on-insulator (SOI) process, and the comparisons are fairly close. TSI has, in fact, been called a "vertical SOI" process because of its similarity to SOI in creating an insulator-based separation between sections of single-crystal silicon. Unlike SOI, of course, TSI goes vertically through the wafer to create islands of silicon joined by insulating bands. In this second way, it is similar to a DI process where dielectrically isolated islands are created on a SOI device layer, which are then used in device manufacture like diode arrays. Unlike DI, though, TSI extends completely through the wafer: the standard thickness for a TSI processed wafer is 430µm, thick enough to be processed through all MEMS or CMOS steps without the need for special carriers or handling. It is this mechanical strength which makes TSI so useful as a wafer level feature.
MEMS is, of course, a mechanical structure and MEMS structures can use the entire bulk of the silicon as elements in its construction. This is unlike ICs which are primarily concerned with the surface 10 or 20μm of silicon area where the circuit elements are formed. And yet MEMS wafers undergo wafer processing which has all the requirements of IC processing (in terms of implants, diffusions, thermal or deposited films, thermal budgets, etc.) plus additional challenges of deep etching, forming complex 3D structures, wafer to wafer bonding, debonding, oxide or silicon release, and noble metal processing. Any TSI process, then, would have to hold up to the full range of processing challenges.
To read more: http://www.electroiq.com/articles/sst/print/volume-56/issue-2/features/cover-article/vertical-through-wafer-insulation-enabling.html