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Apr 4th, 2013
3-D IC stacks pushed back to 2015
Globalfoundries reports on a functioning 3-D wafer-level stack with through silicon vias as the industry pushes out plans for such products to 2015 or later.
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Globalfoundries sees three uses cases for 2.5-D stacks and just one for 3-D using TSVs.
Globalfoundries sees three uses cases for 2.5-D stacks and just one for 3-D using TSVs.

Plans to make 3-D chip stacks for next generation smartphones have been pushed out to 2015 or later. But new chip designs for tablets have emerged using simpler 2.5-D stacking techniques that could ship late next year. 

The good and bad news comes as Globalfoundries announced its first functional wafers with through silicon vias (TSVs) using the 20-nm process at its Fab 8 in New York. TSVs form the connections between chips in a 3-D stack, and Globalfoundries hopes to be an early implementer of the technology. A year ago, Globalfoundries announced it was installing equipment at Fab 8 worth “tens of millions” in hopes of shipping 28- and 20-nm 3-D chip stacks in 2014. Now it says it only expects to use the 20-nm process for 3-D chips that may not ship in volume until 2015 or later.  However, the foundry does appear to be accelerating work in 65-nm at its Singpore Fab 7 on 2.5-D stacks that put chips side-by-side on a silicon interposer for a range of uses.

The 28-nm work got a double whammy in recent months when both Texas Instruments and STMicroelectronics quietly cancelled projects for chip stacks using a first-generation Wide IO memory from Jedec, running at 12.8 Gbits/second.

Other mobile SoC makers are said to be adopting Jedec’s next-generation WideIO spec that will support data rates up to 25.6 Gbits/s and is expected to be finished by the end of the year. They are targeting the 20-nm node, in which Globalfoundries conducted its latest tests.

To read more: http://www.eetimes.com/General/PrintView/4411023



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