Researchers from the Georgia Institute of Technology have won a Defence Advanced Research Projects Agency (DARPA) contract to develop three-dimensional chip-cooling technology able to handle heat loads as much as ten times greater than systems commonly used today.
In addition to higher overall chip heat dissipation demands, the new approach will also have to handle on-chip hot-spots that dissipate considerably more power per unit area than the remainder of the device. Such cooling demands may be needed for future generations of high-performance integrated circuits embedded in a wide range of military equipment.
''There is really no good way to address this heat dissipation need with existing technology, and the problem is getting worse because computing power is increasing and the capabilities being put on chips are expanding,'' says Yogendra Joshi, a professor in Georgia Tech's Woodruff School of Mechanical Engineering and the project's principal investigator. ''There is a real need for developing schemes that can address high power on the whole chip coupled with very high power dissipation areas that are only a few millimeters square.''
DARPA's Microsystems Technology Office, which provided the three-year $2.9 million contract, is seeking techniques to dissipate heat of as much as one kilowatt per square centimeter in the overall integrated circuit, and five kilowatts per square centimeter on smaller areas. The research is part of DARPA's Intrachip/Interchip Enhanced Cooling (ICECool) program.
''The approaches that we are talking about are relatively high-risk,'' says Joshi, who specialises in electronic cooling from the chip-level on up to full-sized data centres. ''They have not been tried before, so there are real questions of reliability – whether they can hold up under repeated cycles of being powered up and powered down.''
In addition to Joshi, the research team includes, Muhannad Bakir, an associate professor in the Georgia Tech School of Electrical and Computer Engineering, who specialises in three-dimensional interconnected systems; Andrei Fedorov, a professor in the Georgia Tech School of Mechanical Engineering, who specialises in understanding and utilising unique physical properties at the nanoscale, and Suresh Sitaraman, also a professor in the Georgia Tech School of Mechanical Engineering, who specializes in evaluating electronic device reliability through innovative characterization techniques and physics-based modeling.
While applications for the high-powered chips aren't specified, their installation in systems intended for field use will add to the level of challenge.
To read more: http://www.domain-b.com/technology/20130405_researchers.html