Researchers aim to ease miniaturization pressure with dense 3-D circuitry instead of stacked chips.
Ever since the integrated circuit made its debut, semiconductors have been “single-story” affairs. But chipmakers are now considering ways to build additional transistor-packed layers right on top of the first. The approach—dubbed monolithic, or sequential, fabrication—could boost the density, efficiency, and performance of logic chips without necessitating a move to smaller transistors. And that could be a boon for an industry that is seriously contemplating the end of miniaturization.
The concept of 3-D circuitry is nothing new. Chips are routinely packaged one on top of another. Nowadays, this packaging is increasingly done using large copper pillars—called through-silicon vias, or TSVs—to vertically connect already-completed chips.
But this prefab approach has its limitations. TSV widths can be measured in micrometers, and that scale is gargantuan compared to the nanoscale features in state-of-the-art chips. That size limits the use of TSVs to fairly low-density connections, such as those needed to join memory and logic together.
In a monolithic 3-D circuit, a chipmaker would simply continue building on top of a 2-D chip, adding an additional layer of silicon on which another set of circuitry could be built. The vertical connections made in this process could potentially be as dense as those found on a 2-D logic chip. If such circuits could be made, chipmakers might be able to avoid all the technical complications associated with shrinking circuitry. “What you win in terms of density, performance, and power consumption is what you would if you had [moved to the] next generation,” says Maud Vinet, manager of advanced CMOS at CEA-Leti, a research institute in Grenoble, France.
To read the full article please click on the following link: http://spectrum.ieee.org/semiconductors/design/the-rise-of-the-monolithic-3d-chip