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Jul 16th, 2008
STMicro advances BSI CMOS image sensors process development
ST’s 3-megapixel back-illuminated image sensor for digital cameras leverages SOI, direct wafer-level bonding and thinning technologies, improving 1.45 x 1.45 µm˛ pixel quantum efficiency over 60% according to a recent article from Advanced Substrate News magazine.
STMicroelectronics has demonstrated the feasibility of manufacturing 3-megapixel CMOS image sensors with a very small pitch (just 1.45µm x 1.45µm) in a back-illuminated design. The company has attained a high quantum efficiency (QE) of >60%. The QE indicates the percentage of photons that are converted into electrons. The back-illumination design starts with an SOI wafer. The company evaluated several SOI thicknesses in order to find an optimal balance between QE and crosstalk.
Mr Roy explained that in a back illumination scheme, you don’t have the problem of the electronics getting in the way of the light’s path; however, the electrons generated by the light still have to reach the photodiode. Different colored lights have different wavelength ranges; blue light for example, which has a short wavelength, is particularly tricky. The longer the photo-generated electrons have to travel, the greater the chance that they’ll diffuse into neighboring pixels, thereby increasing electrical crosstalk. A thicker SOI layer increases QE, but it also increases crosstalk – hence the need for finding the optimal balance.
Lowering dark current
Dark current is essentially leakage current that flows even when the device is not operating. It can really deteriorate image quality badly. As such, it is a challenge in all CMOS image sensors, whether you’re using front or back illumination. Dark current is linked to crystalline defects in the silicon. The quality of the wafer-bonding interface, especially between silicon and the oxide interface, is critical to diminishing dark current. ST has achieved a mean low dark current of 1e/s at 25°C due to dedicated frontside and backside process steps such as a p+ pinning layer and thermal treatment. Other parameters such as conversion gain, lag and temporal noise are comparable to state-of-the-art frontside image sensors.
Manufacturability & Process flow
In STMicro's back-illumination scheme, after the final metal layers are created, a passivation layer and subsequent wafer-bonding layer (WBL) are deposited. The WBL is planarized and a support wafer is bonded to the processed wafer, then thinned through a subsequent grind-back. STMicro has demonstrated the manufacturing feasibility, and is now concluding work related to further cross-talk reduction as well as color filter and micro-lens processing. With this next generation of cell phone cameras, dark and fuzzy snapshots should soon be a thing of the past according to Mr Roy.
The process flow developed involve the use of a SOI wafer. After the CMOS image process, wafer bonding layer (WBL) and surface preparation are realized. Then, final wafer bonding and backside grinding are achieved, followed by the deposition of an anti-reflective coating (ARC). Further to pad opening process, color filters and micro-lens are applied on top of the wafer surface. This achievement leverage the work realized by Tracit Technologies for wafer bonding and thinning studies, CEA-LETI process teams and STMicro front-end technology and manufacturing group
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