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Jun 8th, 2010
 
TSMC reveals plan for 3DIC designs based on Silicon interposers & TSV
 
According to a recent article from EETimes, Silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has expanded its ''platform'' initiative in an effort to speed up new designs in the foundry market. TSMC's initiative, dubbed the Open Innovation Platform (OIP), will now include system-level design, analog/mixed-signal design and 2-D/3-D integrated circuit implementation. The company is putting the pieces in place to enable 3-D designs based on silicon interposers and through silicon vias (TSVs).
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New model for OIP - Open Innovation Platform (Courtesy of TSMC)
New model for OIP - Open Innovation Platform (Courtesy of TSMC)

As part of the effort, TSMC is expanding its efforts in analog. It is introducing a radio frequency reference design kit (RF RDK) and will shortly announce the availability of the analog/mixed-signal (AMS) reference flow 1.0, Reference Flow 11.0.

TSMC originally launched the Open Innovation Platform in 2008 to accelerate designs in the foundry process. This was said to be in response to IBM Corp.'s ''fab club,'' which has been pushing the so-called Common Platform. IBM and its members are developing a common set of process technologies that work across multiple foundries.

TSMC's platform is slightly different. It includes a set of interoperable ecosystem interfaces, collaborative components and design flows. The platform involves more collaboration in the early stages of the IC design process. TSMC's program is aimed to reduce development cycles and manufacturing costs, said Tom Quan, deputy director of design methodology and service marketing at TSMC (Hsinchu).

As part of the new efforts in its platform, TSMC is putting the pieces in place for a 3-D IC design methodology. First, TSMC is developing a design methodology for a silicon interposer technology. Then, it will have a TSV capability.

"TSMC is not offering a silicon interposer or TSV manufacturing capability--yet. It is merely putting together the ecosystem and design tools", Mr Quan said. ''We are putting the pieces in place,'' he said, but ''some of the pieces (for 3-D) are not there.''

Meanwhile, TSMC is adding another new component to the platform: an ESL reference flow. In ESL, the foundry giant is working with Cadence, Forte, Mentor and Synopsys. This effort, in turn, will accelerate the design process and ''connect system-level design to chip-level design,'' he said.

In addition, TSMC is introducing an RF RDK as an outgrowth of an extended Open Innovation Platform. It will also shortly announce the availability of Analog/Mixed-Signal (AMS) Reference Flow 1.0, Reference Flow 11.0.

RF RDK 2.0 targets TSMC's 65-nm RF CMOS process technology. The new design kits implement a top-down RF design methodology and a system-level simulation flow that reduces design cycle time and encourages IP reuse.

The RF RDK 2.0 is in Open Access database that supports new RF design capabilities including a circuit sizing and design centering approach, electromagnetic (EM)-aware RF simulation and analysis, custom RF inductor synthesis and modeling, and substrate noise modeling and analysis (SNA) to address the noise coupling challenges in complex mixed-signal and RF SoCs.

 

 
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