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Sep 10th, 2010
 
Why the secrecy surrounding TSI development?
 
Yole analyst Jean-Marc Yannou describes what’s really going on behind the scenes with through-silicon interposer (TSI) development.
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3D Interposers can solve the reliability issue of low-K dielectrics for high IO density circuits
3D Interposers can solve the reliability issue of low-K dielectrics for high IO density circuits
It seemed like the industry had shifted to an age of collaboration, away from secrecy. But this just isn’t the case with TSI development.
 
As Yannou puts it: It’s difficult to get people to discuss advanced subjects and, in particular, this one.
 
Integrated device manufacturers (IDMs) remain essentially vague or silent on the topic, occasionally publishing forward-looking papers featuring the advantages or challenges associated with 3D silicon/glass interposers.
 
Assembly and packaging service companies (OSATs) and foundries aren’t really publicly discussing TSIs, aside from presenting marketing roadmaps to show that they’re “ready”—without committing any investment capital or capacity production.
 
PCB manufacturers of organic substrates are all looking into TSIs, because the technology is being eyed as a next-gen substrate for some applications. They’d like to get a jump on this and control it, since their primary focus is to sell organic PCBs and it would be nice to keep that business rolling as long as possible.
 
Some small companies and others that aren’t heavily involved in the semiconductor industry, but rather are involved in MEMS, are proposing technology solutions and willing to speak somewhat publicly about their efforts. Surprisingly, many outside the semiconductor industry, especially MEMS packaging and even mechanical glass assembly are proposing using 3D glass interposers and claiming that they can do it at a much lower cost than anything using silicon.
 
So why don’t companies want to talk about their plans for TSIs? There are several plausible explanations why companies are keeping quiet.
 
The benefits of TSIs aren’t proven across all applications,” Yannou says. “Their drivers may differ quite a bit between various applications, and cost remains a serious roadblock for many—even though large performance benefits are expected. For this reason, companies might not want to risk announcing investments for TSI, even though it seems necessary to achieve cost competitiveness.”
 
Another is that the technology “entry barrier” to TSIs isn’t high and many companies are able to develop it. As a result, he notes that there is little interest in industry collaborations, or less interest than for other types of technology under development. Collaboration is now generalized to CMOS developments, and technology differentiation is increasingly expected from packaging, assembly, and mid-end technologies such as TSIs.
 
Because these are relatively simple technologies when compared to CMOS, the question isn’t how to make TSIs; it’s how to use them. The answer is very far from obvious, Yannou believes, because many things need to be considered before making any system-in-package (SiP) choices. This includes: expected electrical and thermal benefits, miniaturization, reliability, cost, alternative technologies, capital investment, and available infrastructure. This can all lead to secrecy surrounding TSIs.   
 
For applications such as MEMS, CMOS image sensors, logic and memory 3D integration, it isn’t yet clear if TSIs will be a long-lasting trend or just a bridge technology waiting for true 3D ICs, much like TSVs in CMOS, to replace them,” says Yannou.
 
What would happen if the industry decided to collaborate? Yannou thinks it would likely spur the needed investments and the adoption of TSIs. “There are already some R&D collaborations between fabless companies and foundries or OSATs or memory companies. They are trying to identify together the opportunities and challenges of TSIs for applications like GPUs and FPGAs,” he adds.
 
At the moment, the biggest question surrounding TSI development is: Will it be a big high-volume deal, a niche technology, or one that is avoided altogether? Yannou doubts it will be a big hit across all envisioned applications, but there will be some applications for it. It’s already being used in CMOS image sensors and MEMS wafer-level capping.
 
And another question on many people’s minds: If TSIs are a bridging technology, waiting for full 3D ICs, how long will the technology be used in high-volume production? And this is quite difficult to predict, he says, but it could range anywhere from three to 10 years.
 

That brings us to cost. Cost is, of course, always a huge issue. No exception here. “When you compute the target cost for a silicon interposer, you need to do it at the complete system level or at least die/package level to find the intrinsic cost of the interposer itself,” Yannou says.

Interested in a universal cost metric for a TSI? According to Yole’s cost simulations, it’s going to need to cost about 1 cent/mm2 or less for a TSI, otherwise it doesn’t stand a chance of becoming a competitive solution. Yannou determined that for an 8-in. depreciated fab that cost target could hardly be achieved, but shifting to a 12-in. fab can drop the cost even further down to 0.87 cent/mm2 —using three metal routing layers and TSVs filled with copper (100µm thickness) and a via diameter of 30µm.

 
(Courtesy of Yole Développement, 3D Glass & Silicon Interposers – 2010 Report)
(Courtesy of Yole Développement, 3D Glass & Silicon Interposers – 2010 Report)
If you’re looking for a much more detailed analysis and a breakdown by application, Yole’s latest report, 3D Silicon & Glass Interposers, delves deeply into the drivers, benefits, target prices, and all critical things that need to be considered, application by application because they’re very different for each one. Notwithstanding the uncertainties inherent to this emerging technology trend, the report even risks presenting wafer forecasts by application.
 

 
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