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Oct 20th, 2010
 
Renesas to commercialize FO-WLP technology in MCU product line by 2011
 
Renesas Electronics Develops FO WLP Package Technology to Realizes Miniaturization at the Bare Chip Level. The New Packaging Technology will be Applied to Microcontrollers, Targeting Product Release in December 2011.
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Process flow for new wafer-level package with fan-out RDL (Courtesy of Renesas)
Process flow for new wafer-level package with fan-out RDL (Courtesy of Renesas)

Renesas Electronics today announced the successful development of a new ultra-compact FO WLP microchip package technology for use in microcontroller unit (MCU) products.

The newly developed technology is a kind of IC packaging technology that employs wafer-level redistribution technology, called the FO-WLP (Fan-Out Wafer-Level Package) technology, which makes it ideal for ultra-compact MCU products. It utilizes multilayer interconnect technology and chip bonding technology, two elemental technologies from Renesas Electronics' SMAFTI™ (SMArt chip connection with Feed-Through Interposer, technology for 3-D IC

The FO-WLP production process consists of:
(1) formation of redistribution layer (RDL) with copper pillar bumps (CPB) on a support wafer,
(2) high-speed chip-to-wafer bonding technology using chips with electroless plated pads,
(3) high-productive wafer-level mold underfilling technology for approximately 10-micrometer (µm) gaps.

Using FO-WLP, Renesas Electronics has succeeded in packaging an 8-bit MCU with a chip size of 1.6 millimeters (mm) × 1.6 mm in a package measuring only 2.0 mm × 2.0 mm × 0.3 mm, a reduction in volume of 80 percent from the previous package size of 3.0 mm × 3.0 mm × 0.7 mm. The two-layer metal interconnects consist of polyimide and copper (Cu), the minimum wire width/space is 15 µm/10 µm, and the interlayer via size is 20 µm.
Test results of the chip-RDL-board electrical connections show excellent reliability in a typical condition of 1,000 −40/+125℃ temperature cycles.

 
Cross-section and images of 2.0 mm x 2.0 mm FO-WLP with 1.6 mm x 1.6 mm chip (Courtesy of Renesas)
Cross-section and images of 2.0 mm x 2.0 mm FO-WLP with 1.6 mm x 1.6 mm chip (Courtesy of Renesas)

The newly developed FO-WLP technology can be used in a new SiWLP® (System in Wafer-Level Package) that enables multiple chips, such as an MCU and an analog/RF IC chip, to be arranged side by side with high-density interconnections between them. It makes possible greater miniaturization and higher integration, allowing multiple chips to be contained in a SiWLP about the same size as a single chip.

With the rapid rise in awareness of energy and environmental issues in recent years, interest is focusing on more efficient use of energy through smart grids as well as environmental sensing and control technologies such as sensor networks. At the same time, sensing and feedback technologies used in patient monitoring systems and the like are becoming increasingly important in fields such as healthcare. SiWLP technology not only makes it possible to produce ultra-compact modules integrating MCUs and analog devices, it also enhances affinity with the environment by combining sensors, actuators, and communication functions needed to implement an interface with the environment or the human body.

Renesas Electronics views the SiWLP technology as a cornerstone in support of advancement of these fields and plans to continue promoting innovative R&D and product development moving forward.


 
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