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Oct 27th, 2010
Xilinx brings 3D TSV interconnects to commercialization phase in digital FPGA world
Based on an innovative 3D silicon interposer design, Xilinx Stacked Silicon Interconnect Extends FPGA Technology to Deliver “More than Moore” Density, Bandwidth and Power Efficiency. This new design breakthrough in semiconductor packaging enables 100x Improvement in Die-to-Die Bandwidth Per Watt and 2-3x Capacity Advantage Over Monolithic Devices.
Xilinx delivers multi-die FPGA breakthrough based on 3D TSV silicon interposers (Courtesy of Xilinx)
This is a major step toward the commercialization of 3D TSV interconnects in digital applications based on "2,5D" silicon interposer. Xilinx, Inc. today announced the industry’s first stacked silicon interconnect technology for delivering breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance. By embracing 3D packaging technologies and through-silicon vias (TSV) for its 28nm 7 series FPGAs, Xilinx’s Targeted Design Platforms can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. This innovative platform approach enables Xilinx to overcome the boundaries of Moore’s Law and offer electronics manufacturers unparalleled power, bandwidth and density optimization for the large-scale-integration of their systems.
"Only two months after we released our latest research report dedicated to 3D Glass & Silicon interposers, this major announcement reinforces our analysis and market forecasts that commercialization of '2,5D' ICs based on interposers is imminent" said Jean-Marc Yannou, Lead Analyst for 3D Packaging technologies at Yole Developpement. Quoting directly the conclusions from his recent report, Jean-Marc added that “This emerging technology trend is definitely more than a myth, and from a niche type of technology, it is already spreading its wings to some high-volume applications”.
Yole Développement is glad to reveal some of the technology details concerning the announcement of this new major leap forward on the steep road of 3D integration at the wafer level. Following today’s press release, Arif Rahman and Patrick Dorsey of Xilinx explained to us that the “Stacked Silicon Interconnect” platform is the result of a five-year research program involving many partners all along the value chain, including TSMC to manufacture the CMOS 28nm FPGA slices and the silicon interposer, and Ibiden for the BGA substrate. The silicon interposers are 100µm thick, and the TSV through vias with diameters of 10µm to 12µm are fully filled with copper. The micro-bumps are Cu-SnAg alloys at 45µm pitch. The interposer itself offers 4 planarized metal layers (3 damascene copper layers and 1 aluminum layer) based on CMOS 65nm technology from TSMC. Xilinx will start sending customers engineering samples of their “Stacked Silicon interconnect” 7 series FPGAs in the second half of 2011. We expect this exciting new step in the emerging 3D wafer-level story to boost and encourage others to follow—not only in the FPGA domain, but throughout the whole digital semiconductor ecosystem, including high-performance ASICs, GPUs, MPUs, digital chipsets and others.
“One of the ways the 28nm Xilinx® 7 series FPGAs extend the range of applications programmable logic can address is by offering industry-leading capacity of up to 2 million logic cells. Our stacked silicon interconnect packaging approach makes this remarkable achievement possible,” said Vincent Tong, Xilinx Senior Vice President. “Five years of Xilinx research and development coupled with industry leading technology from TSMC and our assembly suppliers has made possible our efforts to provide an innovative solution for enabling electronic systems developers to take the benefits of FPGAs further into their manufacturing flow.”
Indeed, FPGAs cannot grow indefinitely large in die sizes or there would be too high a cost penalty due to the negative impact of large die sizes on manufacturing yields. Therefore, when more computation power is needed than can be delivered by a single FPGA of the largest available size built upon the latest CMOS technology node, it is common to place several FPGA packaged parts on a printed circuit board for parallel processing. However, the effectiveness of such architectures is limited by the relatively low bandwidth between two or more adjacent FPGA packaged parts, inherent to the limited I/O routing density and high signal latency between the packages through the PCB.
Thanks to the “Stacked Silicon Interconnect” platform, the FPGA integrated circuits or “slices” as they now may be called are placed closer to one another to reduce latency. In addition, the silicon interposer provides very high routing density, which allows much wider interfaces and bandwidth between adjacent slices than was possible between packaged parts on a PCB. Moreover, since these signals do not need to be driven through long interconnects, the sizes of the I/O buffers can be made considerably smaller, which saves on power consumption and silicon real estate.
In June, Xilinx’s CEO Moshe Gavrielov declared: “In addition to delivering what we and our customers expect from Moore’s Law in terms of capacity and performance with each new generation, we continue our focus on opening programmable logic to a broader audience by delivering design platforms targeted toward the specific needs of new users and markets.”
One could have then read between the lines that something more was being prepared than the next Moore’s law node and its predictable benefits: wafer-level 3D packaging technologies deserve more than the “more than Moore” label. Both these announcements also assert new ambitions and promises for Xilinx FPGAs: to tally the performance of Application Specific ICs (ASICs) for the most demanding applications.
With software support available in ISE® Design Suite 13.1,which is currently available to beta customers, the 28nm Virtex-7 LX2000T device will be the world’s first multi-die FPGA and provide more than 3.5X the logic capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8X the logic capacity of the largest competing 28nm FPGA with serial transceivers. The device is made possible by industry-leading micro-bump assembly, advanced technology from TSMC and patented FPGA architectural innovations from Xilinx that deliver lower levels of power consumption, system cost and circuit board complexity compared to using multiple FPGAs, each in their own package, for the same application.
“Compared with traditional monolithic FPGAs, multi-chip packaging approach is an innovative way to deliver large-scale programmability with favorable yield, reliability, thermal gradient, and stress tolerance characteristics,” said Shang-yi Chiang, Senior Vice President of R&D at TSMC. “By using through-silicon via technology and silicon interposer to implement a stacked silicon interconnect approach, Xilinx expects to reduce risks and is on the way to volume production with well-designed test vehicle runs that meet the company’s criteria for design enablement, manufacturability validation, and reliability assessment.”
Within the Xilinx stacked silicon interconnect structure, data flows between a set of adjacent FPGA die across more than 10,000 routing connections. Compared with having to use standard I/O connections to integrate two FPGAs together on a circuit board, stacked silicon interconnect technology provides over 100X the die-to-die connectivity bandwidth per watt, at one-fifth the latency, without consuming any high-speed serial or parallel I/O resources. By having die sit adjacent to each other and interfaced to the ball-grid-array, Xilinx can avoid the thermal flux and design tool flow issues that would be introduced had a purely vertical die-stacking approach been taken. Xilinx’s choice of 28nm HPL (high-performance, low-power) process technology for the base FPGA device provides a comfortable power budget in the package for integrating FPGA die.
This new architecture will enable High Bandwidth, Low Power FPGA to FPGA Connectivity (Courtesy of Xilinx)
Xilinx stacked silicon interconnect technology serves the most demanding FPGA applications at the heart of next generation electronic systems. The technology’s ultra high-bandwidth, low-latency and low-power interconnect allows customers to implement applications applying the same approaches used for large monolithic FPGA devices, using the software’s built-in auto partitioning capabilities for push-button ease-of use, or hierarchical and team-based design techniques for the highest performance and productivity.
“The Virtex-7 2000T FPGA using stacked silicon interconnect technology is a significant step in FPGA evolution and will enable ARM to implement the latest cores and platform solutions within a single FPGA. This will reduce our development effort, reduce power, and improve performance compared to a multi-FPGA approach,” said John Cornish, EVP and general manager, System Design Division, ARM. “We have been a long time user of the Virtex FPGA technology in the ARM Versatile Express SoC prototyping solutions and this will surely extend our strong position.”
“The availability of proven TSV technology along with low-latency interposer structures is being used effectively by Xilinx to expand the capabilities of their FPGA products,” said Dr. Handel H. Jones founder and CEO of IBS, Inc (Los Gatos, CA). “The technologies used by Xilinx have been used in the high-volume manufacturing environment, with the expectation that the quality and reliability of the finished products will be high, where customer risks are very low.”
A Robust Supply Chain will enable the first proven production of Copper filled TSV in the digital market (Courtesy of Xilinx)
Aligned with silicon progress is a robust supply chain that is in place with leading foundry and outsourced assembly and test partners, including TSMC. Software support will be available in ISE Design Suite 13.1, which is currently available to beta customers. Initial devices will be available in the 2nd half of 2011
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