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Nov 29th, 2010
SET makes strides to enable 3D Integration with high precision Chip-to-Chip and Chip-to-Wafer bonding
SET collaborates with CEA-LETI, STMicroelectronics, ALES and the CEMES-CNRS on advanced chipto-wafer technologies (direct metallic bonding) for 3D integration.
SET collaborate with CEA-LETI, STMicroelectronics, ALES and the CEMES- CNRS on advanced chip-to-wafer technologies (direct metallic bonding) for 3D integration: history & content
Direct copper-to-copper bonding requires a good planarity and excellent surface quality especially in terms of both particulate and metallic contamination. The low roughness of the copper pillars and pad as well as the topology between the copper and oxide areas are critical to obtain good bond at low force and room temperature. The process is developed by CEA-LETI. ALES is supporting some specific developments for the surface preparation. The CNRS-CEMES characterise the bond quality especially concerning the copper structure evolution upon annealing. STMicroelectronics is driving the application of this technology for the high density 3D integration.
SET has developed a “clean” FC300 enabling Die-to-Wafer direct bonding at high yield. The machine operates at room temperature. Special care has been taken for cabling in order to reduce drastically the particle generation. The clean environment inside the machine housing protects the wafer surface while it is fully populated with dice.
What are the advantages of this technology compares to conventional thermo-compression bonding?
SET is very much interested by this direct metal-to-metal bonding which enables fast placement for 3D-IC. It is performed at low force and room temperature which is advantageous for high density interconnect applications requiring high accuracy placement as we do avoid temperature expansion problem. To ensure void-free bonding, the die placement must be carried out in a particle-free environment.
Inside view of the FC300 with direct metallic bonding configuration
JEMSIP-3D: project based on the development of a High speed bonder required for the high volume production of 3D devices using the TSV technology
SET has entered the JEMSiP-3D project to develop a high accuracy, high speed die bonder for the production of devices using 3D technology with high density TSV. The goal is to introduce a die-to-wafer bonder with submicron placement accuracy with stacking capability compatible with “face-to-face” or “face-to-back” alignment. A 2-Step approach with individual placement followed by a global bonding sequence is favoured.
Semi-open confinement substrate for the FC150
Semi-open confinement chamber for oxide removal: principle & advantages
Cu-based systems have become a major focus as an interconnect material for 3D integration. Cu surfaces are bonded together using either die-to-die (D2D), die-to-wafer (D2W), or wafer-to-wafer (W2W) bonding. The oxides present at the Cu surfaces compromise results of thermocompression bonding. To achieve high-quality and reliable bonding, a controlled environment preventing oxide formation during the bonding sequence is required; it is also necessary to remove the oxide that might be present before bonding. Mechanical scrubbing cannot be used when submicron accuracy is needed; therefore SET has developed the semi-open confinement chamber to enable chemical oxide removal without jeopardizing the final placement accuracy. The chamber can be used with forming gas, but efficiency of the oxide reduction is significantly increased by using formic acid vapour. The semi-open confinement chamber includes a substrate chuck and a bond head with a non contact localized confinement which operates safely with reducing gases such as forming gas or formic acid vapour. To preserve the standard capabilities of SET’s bonding tools and especially the low contact force measurement applied to the components, the “Semi-Open” Confinement Chamber has no hardware sealing. A non-contact virtual seal of the micro-chamber enables gas confinement for chip-to-chip or chip-to-wafer bonding under controlled atmosphere. This ensures gas collection and prevents oxygen intrusion while preserving the alignment of the device with respect to its substrate. Consequently, it ensures an excellent wetting and a higher quality of solder joints at reduced bonding forces and temperatures as well as higher yield as no cleaning step is required.
With the confinement chamber, the process gas is injected through horizontal nozzles aimed at the device being bonded. An exhaust ring removes the process gas from the micro-chamber and sends it into the gas exhaust line, keeping the gas out of the machine and the clean room. A nitrogen curtain is formed around the exhaust, ensuring that ambient air is not entrained into the micro-chamber by the Venturi effect, while a deflector attached to the bond head creates the confined micro-chamber. The wafer acts as the deflector for D2W configuration when the chamber is attached to the bond head.
Cross section of three chips stack 3DIC
Yole Développement understands that SET mainly works on accurate placement. What is SET's market positioning with respect to placement accuracy? What are the trades-offs being made to achieve such levels of accuracy?
For over 30 years, SET has been involved in high accuracy applications such as the hybridization of infrared focal plane arrays and the assembly of optoelectronics components required for high bandwidth telecommunication. Both applications require placement within a micron or better. Optoelectronics typically involves components ranging from a few hundred microns in size to a few millmetres, whereas the infrared focal plane arrays can be as large as 100 millimetres. 3D integration with high-density TSV’s requires submicron [or “highly accurate”] bonding, consistent with the accuracy historically required by the IR FPA devices. The primary difference between these two markets is the need for much higher throughput; production of IR FPA’s may be limited to a few tens of devices/day due to extremely long bonding times, while consumer applications of 3D IC may require several thousand bonds/hour. These high throughputs are available on some production bonders, but not at the accuracy or process conditions required by most 3D bonding schemes. SET offers a tool for submicron bonding on 300mm wafers, but with a throughput of only a few hundred units/hour. SET will continue to deliver a high accuracy tool for 3D development and lower volume applications, concurrent to developing a tool with throughputs to meet high volume consumer applications. While many bonding schemes are being investigated around the world for 3D devices, a clear winner has not yet emerged and so process flexibility is still a critical feature. Commercialization of 3D integration is expected to begin perhaps as early as 2012, with higher volume applications ramping up after that.
Populated wafer – Courtesy of IMEC
Several tool designs to meet these market needs are on the drawing boards at SET, always with an eye to meeting the process and throughput requirements of emerging market segments. As noted earlier in this article, a 2-step approach with individual die placement followed by global bonding captures the best features of D2W and W2W bonding schemes; this method is being characterized to identify best practices for pre-attachment. While submicron alignment and positioning of stages and bonding arms will continue to occupy a significant portion of the machine overhead, bonding materials and processes which reduce the temperature and force requirements will likely play a key role in increasing the throughput for 3D applications. For this reason, molecular bonding, performed at modest temperatures and forces, is of great interest. Similarly, polymer bonding is under investigation at IMEC, where SET is partnering with the institute to develop 3D processes using accurate die placement followed by collective bonding in a wafer bonder.
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