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Nov 30th, 2010
STATS ChipPAC’s copper wire bond production exceeds 100 million units with rapid volume ramp
STATS ChipPAC Ltd. (“STATS ChipPAC” or the “Company” – SGX-ST: STATSChP), a leading semiconductor test and advanced packaging service provider, today announced it has shipped over 100 million semiconductor packages with copper wire bond interconnect and expects copper wire bond production volume to grow another 75% by the end of 2010 due to a rapidly growing customer base.
While copper has been used in the semiconductor industry as an interconnect material for many years, there has been a recent surge in demand due to the fact that copper represents one of the most significant savings in material costs available today. The high price of gold has driven a rapid shift to copper as an attractive alternative to achieve cost savings in semiconductor packages. Originally used for low leadcount power devices, copper wire use has now expanded into mid- and high-end Input/Output (I/O) packaging, both leadframe and laminate substrate based, and has been proven on advanced wafer fabrication nodes and fine pitch devices where it offers both a lower cost solution with improved performance. Copper wire provides better conductivity than gold or aluminum, improved electrical and thermal performance, and stronger mechanical properties.
“We are seeing a strong increase in demand for copper wire interconnect in mobile, consumer and computing applications as customers look for cost effective solutions,” said Wan Choong Hoe, Executive Vice President and Chief Operating Officer, STATS ChipPAC. “We have a robust manufacturing process inside a Class 1000 cleanroom environment that is consistently delivering yields comparable to gold wire bonding.”
With five manufacturing facilities in Asia that have copper wire bond capabilities, STATS ChipPAC offers customers a wide range of leaded and laminate packages with copper interconnect and has been actively implementing process capabilities for wafer nodes ranging from 250nm down to 45/40nm with Low-K and ELK dielectric materials. Development work is continuing at a rapid pace on more advanced wafer nodes, finer pad pitches, stacked die packaging and die-to-die bonding.
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