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Dec 3rd, 2010
Semicon Taiwan 3D Forum: Major players reveal current status of 3D IC commercialization
The Semicon Taiwan 3D Technology Forum held in Taipai in September was chaired by Ho-Ming Tong, General Manager and CTO for ASE. Speakers included representatives from UMC, ASE, SIliconware, ITRI, Yole, Nokia, Qualcomm, Verigy, Applied Materials, IME and Sematech.
Several themes emerged from this meeting including: (1) while everyone has bought into the inevitability of 3D IC the lack of standardization seems to be gating adoption of the technology; ( 2) everyone’s roadmaps now look remarkably alike which either means that we are reaching consensus on timing or that they are being made to intentionally all look alike so no one looks like they are behind; (3) there also appears to be general buy-in on “2.5D” (the 3D interposer) since it will be used to “bridge the gap” to 3D IC and because it will be needed in order to package 32 and 22 node CMOS chips in the near future; (4) the big driver application looks like it is wide I/O memory and logic; (5) there still is not a clear division of labor between the foundries and the assembly houses; and lastly (6) now that manufacturers are looking at HVM process details technical issues are becoming more apparent (although most of them look like engineering issues that simply need to be worked through).
Chien predicts that DRAM stacking will be seen in the 2009 – 2011 timeframe, logic + wide I/O DRAM stacking will occur in 2011-2012 and heterogeneous stacking like Rf + DRAM +ASIC will be seen sometime following that.
UMC reveals that they are finding vias middle scaleup problems such as Cu TSV extrusion, Cu voiding, oxide liner cracking and interface ILD cracking which have led them to take anther look at vias last (from the backside).
When it comes to memory stacking, Kauppi Kujala, Sr Tecnology Mgr at Nokia reports that TSV can offer “..clear miniaturization opportunities (and) also performance and power reduction”
Like many others in the field, Nokia agrees that the main driver will probably be wide I/O memory mating with memory starved logic devices. Nokia preference and first target for Wide IO package is a single package with 4 DRAM with “.. High end smart phones are initially driving the development. Migration to mid segment and lower categories will follow later”
Vs PoP, wide I/O memory stacking with TSV is expected to deliver 35% package size reduction, 50% power consumption reduction and 8X the bandwidth.
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