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Dec 9th, 2010
On Semiconductor low profile CSP for mobile products
Supplying the smart phone marketplace is requiring components to become thinner and thinner. Umesh Sharma of On Semiconductor indicates that “…In thin smart phone products, the space between the cable and the board is so small that only ultra-thin IC or discrete components could be placed in that location of the PCB.”
To meet such a 0.275 mm thickness objective, ON Semiconductor has been developing “LP-CSP” a low profile CSP (WLP). The LP-CSP is manufactured by wafer level processing. Including UBM deposition and patterning over the I/O openings, solder ball placement and reflow. The silicon wafer is subsequently background to meet the final desired LP-CSP thickness.
Sharma indicates that WLCSP I/O pitch, for mobile applications, has decreased from 0.65 mm to 0.40 mm during the last decade. As the I/O pitch reduced from the 0.65 mm to 0.40 mm, the solder ball size has decreased from 0.35 mm to 0.25mm. As shown in the figure below, while the ball pitch has decreased by 33%, the total thickness has changed only 12%. These are compared to the new LPCSP below:
The goal of 0.275 mm thickness could only be achieved by reducing the ball height and/or the silicon wafer thickness. A silicon thickness of 200 um was chosen because of “..the current limits of automated handling equipment used in the wafer level processing” Since it is well known that increased solder ball height increases reliability, thinner silicon was required to offset this effect.
Physical data and Reliability on LP-CSP
Sharma concludes that the LP-CSP technology “…does not require special assembly handling, additional assembly steps or underfill”. It is clear from the data that both silicon thickness and bump height reduction are necessary to ensure board level reliability performance of the LP-CSP is comparable to WLCSP.
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