webleads-tracker

Home  >  ADVANCED PACKAGING  > On Semiconductor low profile CSP for mobile products...
  >  ADVANCED PACKAGING
Dec 9th, 2010
 
On Semiconductor low profile CSP for mobile products
 
Supplying the smart phone marketplace is requiring components to become thinner and thinner. Umesh Sharma of On Semiconductor indicates that “…In thin smart phone products, the space between the cable and the board is so small that only ultra-thin IC or discrete components could be placed in that location of the PCB.”
Send to a friend

To meet such a 0.275 mm thickness objective, ON Semiconductor has been developing “LP-CSP” a low profile CSP (WLP). The LP-CSP is manufactured by wafer level processing. Including UBM deposition and patterning over the I/O openings, solder ball placement and reflow. The silicon wafer is subsequently background to meet the final desired LP-CSP thickness.

Sharma indicates that WLCSP I/O pitch, for mobile applications, has decreased from 0.65 mm to 0.40 mm during the last decade. As the I/O pitch reduced from the 0.65 mm to 0.40 mm, the solder ball size has decreased from 0.35 mm to 0.25mm. As shown in the figure below, while the ball pitch has decreased by 33%, the total thickness has changed only 12%. These are compared to the new LPCSP below:

The goal of 0.275 mm thickness could only be achieved by reducing the ball height and/or the silicon wafer thickness. A silicon thickness of 200 um was chosen because of “..the current limits of automated handling equipment used in the wafer level processing” Since it is well known that increased solder ball height increases reliability, thinner silicon was required to offset this effect.
Data on the LP-CSP is shown below. Board Level Temperature cycling  (BLTC) and Board Level Drop Test (BLDT) studies wre done to insure reliability. BLTC was done up to 1000 cycles with a temperature range of 125°C to -40°C and a 30 min cycle time. BLDT condition were 1500G and 0.5ms half width duration up to 1200 cycles. HAST conditions were standard 130°C, 85%RH and 96 hr. The devices were electrically tested before and after HAST.

Physical data and Reliability on LP-CSP

Sharma concludes that the LP-CSP technology “…does not require special assembly handling, additional assembly steps or underfill”. It is clear from the data that both silicon thickness and bump height reduction are necessary to ensure board level reliability performance of the LP-CSP is comparable to WLCSP.
The photograph below compares the LP-CSP with an equivalent WLCSP die. The LP-CSP height is 0.265mm and the WLPCSP height is 0.58mm. The LP-CSP device height is more than 50% thinner than
the standard WLCSP device.


 

 

 
More ADVANCED PACKAGING news

Jul 31st
Jul 30th
Jul 29th
Jul 23rd
Jul 22nd
 
©2007 Yole Developpement All rights reserved                  Disclaimer | Legal notice | To advertise
Yole Développement: Le Quartz, 75 cours Emile Zola, 69100 Villeurbanne, France. TEL: (33) 472 83 01 80 FAX: (33) 472 83 01 83 E-Mail: info @yole.fr