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Jan 3rd, 2011
 
Samsung, Elpida and Tohoku Univ Discuss 3D IC at RTI Conference
 
At the recent RTI 3-D Architectures for Semiconductor Integration and Packaging Conference in Burlington CA we had the chance to discuss 3D technology with experts from Samsung, Elpida and Tohoku University.
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This past summer Elpida announced that it will use it’s 3D technology to “expand beyond its DRAM business” and that it had partnered with UMC and Powertech to deliver a “total 3D IC memory + logic solution”. Ikeda-san, principle professional at Elpida indicates that the partnership was/is needed to satisfy infrastructure requirements, “…the partnership can take responsibility for the final stacked device …without the partnership, responsibility would be very difficult”.

Hiroaki Ikeda (Elpida), Mitsumasa Koyanagi (Tohoku Univ), Tae-Je Cho (Samsung) and Sungdong Cho (Samsung)

Ikeda is a supporter of silicon interposers or “2.5D”. He agrees with the recent UMC announcements that there will likely be two classes of interposers; (A) high density interposers manufactured by front end fab technology (i.e. 1 um technology) for high density I/O requirements (i.e. 4000 I/O / interposer) and (B) lower density interposers, manufactured by thin film packaging technologies, for single or multiple chip solutions that can be satisfied by 5-10 um L/S. He feels 2.5D will require a “stiff carrier… probably 200 um thick silicon”.

When asked about the recent ASET publications looking at 10 um thick 3D IC technology he offered that these were “challenging goals” and commented that 10 um thick Si with bumps on each side, that are likely offset (not directly under each other) are very fragile and difficult to assemble. Ikeda indicates that Elpida will initially stay with backside copper TSV on 50 um thick silicon. “Backside copper TSV in 50 um silicon give far less issues with stress and copper contamination that Professor Koyanagi has been discussing lately”.

Koyanagi-san, who in his earlier days studied memory device architectures for Hitachi, is a well-known veteran in 3D technology having worked in the area for more than a decade  [see : “Future System-on-Silicon VLSI Chips” in the IEEE Computer Society’s “IEEE Micro” (1998) for instance].
Koyanagi and co-workers from Tohoku University have more recently been examining the electrical implications of mechanical stress / strain and metal contamination on thinned 3D LSI.
Cu and Au are known to seriously degrade the carrier lifetime and hence device characteristics. To suppress such metallic impurity diffusion, fabs have employed both intrinsic gettering (IG) and extrinsic gettering (EG). When dealing with 3-D IC these gettering regions must be designed properly so that they are not removed by wafer thinning” notes Koyanagi.

We have been analyzing the induced strain/stress and crystal quality after wafer thinning by micro raman spectroscopy (μRS) and XPS respectively and the local stress induced by metal microbumps after die-to-die/wafer-to-wafer bonding using μRS, and the impact of induced local strain/stress on device performance”. Both CMP and dry polishing (DP) were examined to relieve the stress after backside thinning. They found that the backside was under strain but that the strain in the CMP treated sample is quite low as compared to DP method concluding that...the DP method is not suitable for the stress-relief process in 3D wafers”. The magnitude of strain increased with the decrease in wafer thickness. On the other hand Koyanagi points out that “... the backside surfaces treated by the DP method exhibited more effective EG for metal contamination than the CMP treated backside surfaces…thus optimization is needed to balance the wafer thickness, the stress relief and the EG effect

For fine-pitch microbumps Koyanagi notes that “…as the die cools down after bonding, the copper shrinks more than the silicon substrate due to CTE miss match, thus the copper bump compresses the silicon die.” When the Cu/Sn microbumps compressive stress extends more than 10 um deep, comparable to the depletion region thickness, it is expected to have an adverse impact on device characteristics”.

Tae-Je Cho, master, and Sungdong Cho, Sr engineer are part of the System LSI division at Samsung. A few weeks ago the memory division announced commercial production of two chip memory stacks with TSV for high performance server applications.
 In his presentation at the RTI conference, S Cho indicated that there will be two 3D TSV platforms for the systems LSI group: Interposer and memory on logic. For the memory on logic technology they are developing copper TSV middle technology.
(1) High AR TSV filling, (2) Cu extrusion, (3) Stress impact on devices and (4) Copper contamination were specifically listed as 3D challenges. Cho indicates that they will not use W because of the severe wafer bow that even 1 um of W imparts to a 300 mm wafer. They also see “severe Si cracking and IMD cracking due to the high W stress”.

They have seen “severe copper extrusion and delamination after copper anneal / CMP and before BEOL IMD deposition”. They find that the best solution is “...via size and depth reduction” and indeed report they have found processing space (via depth vs via diameter) to minimize such problems. 

Cho reports that they are also closely examining  copper contamination issues both due to copper leakage through poor TSV liners and the backside thinning and processing issues brought up by Professor Koyanagi.

 

 
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