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May 23rd, 2011
3D integration and Advanced Packaging Programs at SEMICON West
This year’s 3D integration and Advanced Packaging Programs at SEMICON West, July 12-14, 2011, in San Francisco, CA, are shaping up to be real crowd pleasers.
The SEMI Advanced Packaging Committee, chaired by Bill Chen, ASE Fellow, has been hard at work making sure all bases are covered in this expanding market sector from 3D integration, heterogeneous integration of MEMS and sensors to the latest in ‘contemporary’ packaging and wafer-level packaging (WLP) processes. In fact, so much ground to cover called for the expansion of the original time slots.
Divided on three different stages over two days, this year’s programs will follow a keynote/panel discussion format with representatives from across the supply chain assembled to discuss challenges and solutions for each focus area.
Heterogeneous Integration with MEMs & Sensors (Tues. July 12 2:00pm–4:30p)
Contemporary Package Challenges and Solutions for 40nm and Beyond (Wed. 10:30am–12:30pm)
Co-Chaired by Tom Gregorich of MediaTek and Rich Rice of ASE, the keynotes will be delivered by Sanjeev Sathe, GLOBALFOUNDRIES and Jim Walker, Research V.P. Gartner. Panelists include Doug Yu, Sr. Director of Interconnect and Packaging, TSMC; Mike Ma,V.P, R&D, Siliconware Precision Industries Co., Ltd (SPIL); and Fernando Chen, Senior Director, Laminate Products & Technology Marketing, STATS ChipPAC.
3D in the Deep Submicron Era (Wed. July 13, 1:30pm–5:00pm)
Session chairs Jie Xue, Cisco, and Gamal Refai-Ahmed, AMD, are organizing a group of experts on these topics to address these specific questions and concerns. Divided into two sub-sessions, the first will address 2.5D integration using silicon interposer technology, and will kick off with a keynote address from industry visionary, Vincent Tong, Senior VP at Xilinx. followed by a panel discussion co-moderated by Sitaram Arkalgud, 3D IC program director at SEMATECH and John Lau, Electronics & Optoelectronics Labs, ITRI. Confirmed panelists include Rao Tummala, of Georgia Tech’s 3D Packaging Center; Ron Huemoeller, Senior VP, Advanded 3D interconnects, Amkor; Jon Greenwood, Senior Member of Technical Staff, Technology & Integration GLOBALFOUNDRIES, and Stephen Pateras Product Marketing Director, Silicon Test, Mentor Graphics.
The second session will feature a keynote by well-known market and technology analyst, Jean-Marc Yannou, of Yole Developpment. The ensuing panel discussion, 3D Packaging Technology and Ecosystem, co-moderated by Hirofumi Nakajima, Senior Manager, Packaging & Test Technical Strategy, Renesas; and Steve Bezuk, Director of Engineering, Qualcomm; will examine the state of the 3D market and its remaining hurdles. Confirmed panelists now include Bill Bottoms Chairman and CEO Third Millennium Test Solutions, Inc. (3MTS); Rozalia Beica, Global Director of 3D Interconnect Technology Transfer and Integration of Applied Materials; and Calvin Cheung VP of Engineering, ASE U.S.
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