The SEMI Advanced Packaging Committee, chaired by Bill Chen, ASE Fellow, has been hard at work making sure all bases are covered in this expanding market sector from 3D integration, heterogeneous integration of MEMS and sensors to the latest in ‘contemporary’ packaging and wafer-level packaging (WLP) processes. In fact, so much ground to cover called for the expansion of the original time slots.

Divided on three different stages over two days, this year’s programs will follow a keynote/panel discussion format with representatives from across the supply chain assembled to discuss challenges and solutions for each focus area.

Heterogeneous Integration with MEMs & Sensors (Tues. July 12 2:00pm–4:30p)
With double-digit growth forecast for the MEMS industry, more MEMS devices and sensors are finding applications in the global market place. Smart phones, handheld gaming devices and consoles, and automotive applications are leading the charge. With devices on the market ranging from pressure sensors, RF‐MEMs, accelerometers and gyroscopes, to microphones, micro‐actuators, compasses, CMOS image sensors, chemical sensors, microfluidics, and mirrors and displays, there’s no doubt that MEMS are growing fast. To paraphrase ITRS, the intersection of Market and Technology is calling for “More MEMS and More Than MEMs”. This session will focus on key players in the system, device manufacturer, OSAT and consortia segments of MEMS. Chaired by Klaus-Dieter Lang, Fraunhofer - IZM Director, keynote speeches for this session will be delivered by Raj N. Master, General Manager, IC Packaging, Quality & Reliability Microsoft; and market analyst, Jan Vardaman, president, TechSearch International. Confirmed panelists include M. Juergen Wolf, Fraunhofer IZM,Yoshiaki Sugizaki, Toshiba Corp, and Gilles Poupon, CEA-Leti. They will be joined by several other representatives from across the MEMS and packaging ecosystem from academia through the supply chain.

Contemporary Package Challenges and Solutions for 40nm and Beyond (Wed. 10:30am–12:30pm)
Much has been written about emerging technologies for the 40nm fab node (and beyond), such as CU pillar FC, ELK compatibility and 3D TSV. However, product-level applications for these technologies tend to focus on performance-driven market segments; markets which are better-able to fund technology development and can accept higher initial risk. But what about market segments which account for up to 70% of our industry and which are driven largely by low-cost and low-risk? Are cost-effective IC package solutions available for market segments such as handheld, consumer and automotive as they migrate to smaller silicon lithographies in search of cost reduction? When faced with the decision to use an advanced fab node, will these companies:
• Change package interconnect technology?
• Change package and PCB technologies?
• Change system architecture?
• Adopt new technologies such as FO-WLP and TSV?
• Continue to use the existing fab node
• Do something else?

Co-Chaired by Tom Gregorich of MediaTek and Rich Rice of ASE, the keynotes will be delivered by Sanjeev Sathe, GLOBALFOUNDRIES and Jim Walker, Research V.P. Gartner.  Panelists include Doug Yu, Sr. Director of Interconnect and Packaging, TSMC; Mike Ma,V.P, R&D, Siliconware Precision Industries Co., Ltd (SPIL); and Fernando Chen, Senior Director, Laminate Products & Technology Marketing, STATS ChipPAC.

3D in the Deep Submicron Era (Wed. July 13, 1:30pm–5:00pm)
3D is about much more than 3D‐IC and Moore’s Law Scaling. The drive for 3DIC has spawned a whole ecosystem for TSV technologies ranging from industry, academia, and research institutes to equipment and materials suppliers. Silicon interposers based upon TSV — thus inspiring the term 2.5D — have become critical in the first wave of 3D implementation. From high-performance network systems and servers to laptops, tablets, mobile systems and game consoles, the silicon interposer represents a solid fork in the highway for 3D implementation, thus raising the questions: What is the silicon interposer ecosystem? Is the industry infrastructure in place for high-volume cost-efficient 3D implementation? What will the next step be? In the world of “More Moore and More Than Moore”, 3D silicon interposer technology enables the industry “to have its cake and eat it too”.

Session chairs Jie Xue, Cisco, and Gamal Refai-Ahmed, AMD, are organizing a group of experts on these topics to address these specific questions and concerns. Divided into two sub-sessions, the first will address 2.5D integration using silicon interposer technology, and will kick off with a keynote address from industry visionary, Vincent Tong, Senior VP at Xilinx. followed by a panel discussion co-moderated by Sitaram Arkalgud, 3D IC program director at SEMATECH and John Lau, Electronics & Optoelectronics Labs, ITRI. Confirmed panelists include Rao Tummala, of Georgia Tech’s 3D Packaging Center; Ron Huemoeller, Senior VP, Advanded 3D interconnects, Amkor; Jon Greenwood, Senior Member of Technical Staff, Technology & Integration GLOBALFOUNDRIES, and Stephen Pateras Product Marketing Director, Silicon Test, Mentor Graphics.

The second session will feature a keynote by well-known market and technology analyst, Jean-Marc Yannou, of Yole Developpment. The ensuing panel discussion, 3D Packaging Technology and Ecosystem, co-moderated by Hirofumi Nakajima, Senior Manager, Packaging & Test Technical Strategy, Renesas; and Steve Bezuk, Director of Engineering, Qualcomm;                will examine the state of the 3D market and its remaining hurdles. Confirmed panelists now include Bill Bottoms Chairman and CEO Third Millennium Test Solutions, Inc. (3MTS); Rozalia Beica, Global Director of 3D Interconnect Technology Transfer and Integration of Applied Materials; and Calvin Cheung VP of Engineering, ASE U.S.

This agenda is still subject to change. Stay tuned for program updates on 3D InCites (www.3Dincites.com). Details can also be found at www.semiconwest.org.