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Jan 8th, 2013
IMECs Marinissen discusses 3DIC wafer testing: A Closer Look
In the pre conference symposium at the recent RTI sponsored 3D Architectures for Semiconductor Integration and Packaging ( 3D ASIP) conference Erik Jan Marinissen of IMEC gave an in depth look at the state of 3D stack testing . i-Micronews felt it was worth “ a closer look”.
The 3 main questions he asked and then answered were:
The degree of testing has to be looked at as a cost/benefit tradeoff which will look at the yield and the % of the bad product that the testing could have detected.
Fine Pitch uBump Probing
Testing of IMEC standard structures involves 15 um bumps on 40 um pitch and bottom bumps are 25 um on 50 um pitch.
IMEC top and bottom pad dimensions
KGD testing is usually done on dicing frames, but for thinned wafers most probers cannot handle the sagging. Marinissen reveals that TEL now offers automated handling and probing of 300 mm wafers on dicing frames.
Design for test (DfT) is used for prebond, post bond and post packaging testing.
Design for test
As an example, Marinissen shows the results of IMEC consortium partner TSMC’s testing of logic + memory structures.
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