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Jun 29th, 2009
3D Integration for wireless products: An industrial perspective
The mobile phone and wireless industries have been growing at a very fast pace in the last 10 years. With more than 1.2 billion phones sold in 2008, the wireless market has been one of the main contributors in driving the development of the most advanced semiconductor technologies. The computing power for portable devices is becoming mandatory to enable mobile internet browsing, mobile TV, and all increasing multimedia features. In that context, miniaturization and performance are the driving forces for silicon technology development.
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Following the ITRS roadmap with CMOS downscaling is the traditional way to proceed. But the R&D expenses to sustain such a roadmap are extremely selective. Only a few companies or consortia can afford it. That’s why advanced CMOS technology could start to be seen as a kind of commodity and integration with new solutions appears as a much stronger differentiator element. Packaging contributions in the final product gained in importance. Major improvements and progresses have been done lately and a new solution is gaining more and more importance: 3D Integration.
3D Packaging
Fig 1: FOWLP 1 side (left) , 2 sides (called 3D-eWLB, right)
Fig 1: FOWLP 1 side (left) , 2 sides (called 3D-eWLB, right)
Despite the recent buzz in the industry for a couple of months, 3D configurations are not new at all. In effect, 3D configurations at the packaging level have been around for years. In many teardowns of handsets, lot of 3D packages can be found. A stack of dice with wire bonds is something very common for memories. Package over Package (PoP) or Package in Package (PiP) is a configuration widespread to combine the stack of memories on top of an application processor or digital baseband. At the same time, 3D package solutions such as embedded die in laminate or rebuilt wafer such as Fan-Out Wafer Level Packaging (FO-WLP) are emerging. FO-WLP goal is to construct a package as small as possible to enable all the BGA balls to fit on it. The packaging is built around the individual known good die and provides a way to make the laminate substrate vanish. FO-WLP improves signal integrity, shortens interconnects, reduces line/space for rerouting, and as a consequence, allows a reduction in the package footprint. Infineon and Freescale developed their own FO-WLP technology respectively called eWLB and RCP. Lately, STMicroelectronics partnered with Infineon and STATS Chip Pac to develop the 2nd generation of eWLB, 3D-eWLB, and enable 2-sided and consequently, 3D configurations.
3D at IC level using TSV
Fig 2: From design to packaging: demonstration<br> achieved between STMicroelectronics and CEA-LETI
Fig 2: From design to packaging: demonstration
achieved between STMicroelectronics and CEA-LETI
All the configurations mentioned above are 3D at the packaging level. None of them uses TSV, which could allow “real” 3D at the IC level in some configurations. TSVs are nothing more than a techno brick that allows dice to interconnect on the vertical axis at the IC level. The impact of TSV is that these short interconnections could enable a new split of functions and new product partitioning. However, it is important to notice that TSV interconnections can be done at different levels and the impact on final applications is not the same. Either the TSV is done at the bond pad level or at the global interconnect level.

At the bond pad level, TSV is done in a via last process in a wafer level packaging fab environment. The pitch of TSV is in the range of a bond pad pitch. Typical values from 50 to 150µ in term of pitch can be considered. An aspect ratio can reach 5:1 and filling is conformal or full. RLC electrical performances are better than wire bonds, except for the capacitance that may remain high. This type of TSV can be based on an improvement of technologies developed for CIS.

At the global interconnect level, we consider TSV with higher aspect ratio done in foundry environment, preferably via middle (after FEOL but before BEOL) or first (before FEOL). TSV pitch is in the 10-20µ range with the aspect ratio ranging from 5:1 to 10:1 or even a bit more. For this category of TSV, dice are not only connected at bond pad level but also at the IP block or memory bank levels for instance. This type of TSV enables the achievement of structures with very short interconnections and good electrical performances. True heterogeneous integration is made possible and SoC–like features can be realized but using the third dimension and not only the x-y directions. Dice interconnected with this type of TSV are closer to SoC than SiP. For these reasons, 3D SoC is a very good term for this configuration. Figure 2 shows key demonstration achieve in STMicroelectronics with CEA-LETI.
Complementarity of 3D packaging and 3D IC
Fig 3: 3D IC TSV stack in 3D-eWLB (Courtesy of ST-Ericsson)
Fig 3: 3D IC TSV stack in 3D-eWLB (Courtesy of ST-Ericsson)
Except for some wafer-level chip-scale packages (WLCSP) or silicon interposer with TSV directly mounted on Printed Wiring Board (PWB) with a BGA balls, TSV is not a packaging solution by itself. TSV uses only “back-end world” skills such as bonding, fine pitch bumping, back grinding and thin wafer handling, for instance. In effect, final packaging is required to connect the device to the PWB. And due to assembly constraints, the choice of the final package solution could impact the entire TSV process flow. This final packaging could be a BGA package, a Fan-Out WLP type, an embedded die in laminate, or other. Here, it is interesting to notice how complementary 3D IC configurations with TSV and 3D packaging can be. In effect, 3D eWLBTM can enable designs to fully benefit from the 3D IC integration, and for instance, reduce the package footprint with more aggressive design rules than BGA packages. TSV is a new technology and 3D eWLBTM a new packaging technology as well. Only considering BGA-type packages for structures with TSV might be a wrong reasoning. Some constraints can even be relaxed by coupling 3D IC TSV with 3D advanced packaging and then the full benefits of the TSV can emerge. Issues such as thin wafer handling can, for instance, be simplified.
3D Integration: Convergence of Architecture with Silicon & Package and Out of the box thinking required!
3D IC TSV is the convergence of silicon and packaging with the design. New architectures can in effect be considered and achieved. In fact, new architectures have to be considered if cost effectiveness is to be reached.

In order to fully benefit from 3D TSV and make this technology cost effective, 3D architecture needs to be considered at a very early stage. However, designers are facing a gap between TSV technology process and TSV system design. This gap is due to the fact that there is no clear TSV technology roadmap in the industry. With a scaling-based approach and a classical follow-up of Moore’s law, it was easier to focus the R&D efforts and predict the size and performance of a new techno node. With 3D TSV, the industry is facing a new paradigm. Designers’ mentalities have to be modified and the former constraints of 2D have to be partially forgotten.

Roadmaps exist, but are not necessarily very relevant. For this reason, many options can be considered, and process technologists do not know by themselves where to go and on what to focus. The only solution is to reinforce collaborations and discussions between the design community and the hardware technology community. A holistic approach is necessary to find the technology / design sweet spot and the application needs to drive developments.
Application roadmap
Fig 4: Application Roadmap for 3D integration <br> in wireless products (Courtesy of ST-Ericsson)
Fig 4: Application Roadmap for 3D integration
in wireless products (Courtesy of ST-Ericsson)
Applications that could use TSV and 3D remain a hot question. Only a few people have clear views on products that could use such innovations. Many niche markets would exist, for sure. However, when we think about core chipset components in wireless, the scope of applications tends to reduce. The following roadmap is based on ST-Ericsson’s and STMicroelectronics’ view and portfolio for wireless products (fig 4). Memory stacks with TSV such as DRAM are not mentioned as they are not part of the company business area anymore. Combinations of 3D IC TSV with advanced packaging such as 3D eWLB are not detailed on the schematics.

The first CMOS Imaging Sensors are now on the market and ramping up. The possibility to substitute wires by connections coming from the backside of the die would gain them a reduction in the camera volume and its cost. However, in this example, we can’t speak about TSV enabling 3D configuration because, in fact, no chips are connected along the vertical axis. The top layer is only a glass carrier, not an active die; this can be called 2.5D but definitively not 3D.

Power Amplifiers (PA) built in SOI are likely to use TSV technology in the future in order to improve performance and reduce die size. For PA, TSV is only used for parasitic and each is connected to a common ground on the metallized backside of the chip. Wires remain for I/O. In that case, a very low cost TSV technology is compulsory. Thermal dissipation improvement is foreseen as well.

The first true 3D ICs using TSV are forecasted for 2012. New partitioning of chips with IP in the best techno node will appear. Logic dice would be from different techno node generations (N generation, N+1, N+2…). A smart split of functions will be done in order to achieve the right cost/performance trade-off with TSV as the new enabler. An intermediate step based on a silicon interposer for the bottom die, containing only routing and few functions, is likely to happen. It will help in bridging the gap toward 3D SoC and a full readiness of design tools. With 3D IC and TSV, new topics will need to be considered. Numbers of options in silicon wafers, such as the type of ESD protection and test strategy are a few. A key advantage of 3D IC for this scheme of integration is clearly the time reduction of critical IP development in an advanced techno node. With a smart partitioning, complexity will be reduced and no longer on the critical path.

A memory / logic stack using TSV is a type of application the industry often refers to. The main reason for this is the increased bandwidth required by the final applications (driven by video features such as 1080p30 playback, 1080p30, 60, 120 Camcorder, 3D gaming…). With a new memory / logic interface architecture, based for instance on a wide I/O approach, this bandwidth challenge might be overcome. Furthermore, this new wide I/O interface with parallel access to the memory will enable lower power consumption in the memory bus. For cellular phones, this bandwidth bottleneck might come after the Low Power DDR2 memory generation. However, many challenges are rising. Thermal management is definitively a critical point in this approach. In effect, the power dissipation of the logic die, typically an application processor or a digital baseband, can heat the memory directly stacked on top. As memories have a lower Tj than logic die (85°C or 105°C), the memory will receive too much heat and won’t work correctly. Power dissipation of the bottom die will be range from 1 to 3 W from low to high end 3G platforms.

Another main issue with the wide I/O memory is the standardization and supply chain. Most of the time, the memory and logic die will come from different companies. Standardization will be required to enable the final OEM integrator to source different memory types or any double sourcing.
Roadmaps will mature during the next few years as people begin to understand all the capabilities of 3D Integration. As of today, only the emerging part of the iceberg is visible. 3D thinking is only at its early beginning and much more will be discovered and understood in up-coming years. The only thing to avoid with 3D Integration is to continue thinking based on the past experiences of downscaling. Applying Moore’s law based on scaling to a More than Moore approach such as 3D Integration TSV is not necessary at all. The application should help in the roadmap definition.

It is crucial to differentiate 3D packaging and 3D at the IC level using TSV. TSV by itself is not a packaging technology apart from some few exceptions. Consequently, 3D TSV and 3D packaging do not have to be considered as competitors but more as complementary areas. In recent years, the semiconductor industry has expressed some growing interest in these ideas and put some significant efforts in allowing the emergence of these new breakthrough technologies. Still, some challenges remain ahead for a wide adoption. Most of them are cost, a shift in the design method paradigm, system co-design, new CAD tools, new architectures, and more new challenges. The 3D IC TSV combined with the 3D eWLB appears as the next wave for future integration and should initiate some new integration schemes. We expect to expand the innovation landscape through lower cost and better electrical and thermal performances enabled by new partitioning and architectures, higher flexibility, better integration with easier software implementation and a shorter time to market.
Yann Guillou is currently in charge of New Technology Marketing activities for the Wireless Multimedia Group of ST-Ericsson. His main interest is in 3D Integration and Advanced Packaging. He started his career at CEA-LETI before joining STMicroelectronics and successively worked at ST-NXP Wireless and ST-Ericsson. He holds a MSc degree in Materials and NanoTechnology from INSA (National Institute of Applied Sciences, France) and a Specialized Master in Management of Technology and Innovation from Grenoble Business School (France).


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