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May 27th, 2013
“Quilting” technology: A closer look
In the silicon MCM technologies of the 1990’s [1] the goal was to get chips as close together as possible to achieve the shortest interconnect distance and thus the fastest signal propagation.
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While a significant advantage over other packaging and interconnect options of the time, signal transfer in MCMs was still from chip 1 to interposer substrate to chip 2.   Signal transfer from chip 1 to chip 2 without going through a substrate was always the holy grail.
Quilt Packaging® technology does exactly that. Developed by Gary Bernstein and several others at University of Notre Dame ~ 2003 [2], this technology was spun out as Indiana Integrated Circuits (IIC) in 2009. iMicronews felt this technology is worth…A Closer Look

Quilt Packaging potentially allows for:
- integration of disparate materials and process technologies
- chip partitioning for optimal yield and process optimization
- security, i.e. fabrication of different segments at different fabs
- design advantages due to the applicability of current 2‐D tools
- non standard chip geometries (hexagonal or other shaped die ) can be utilized since the constraints of using a wafer saw are eliminated

QP is an edge interconnect scheme that uses  metal “nodules,” built on the edges of the chips to electrically mate them along their edges.. The core principle of Quilt Packaging technology is the fact that it enables multiple ICs to be integrated into a larger "die" that performs essentially as if it were monolithic.
The mating nodules are subsequently soldered to each other. The completed quilt (see below) is then treated as if it were a single IC, is placed in a IC package and connected in a conventional manner, e.g. by wirebonds or solder bumps for interconnection to the system.

Schematic of 3-die quilt mounted on paddle of plastic package

The metallic nodules are typically 10-200µm wide and 20-50 µm thick. Customizable interlocking shapes, such as the one shown below allows for sub micron chip alignment  and adds further structural stability.  This typically results in a chip to chip ~ 15 µm gap post soldering. 

Quilting Connections : (left) interlocking configuration [3]; (right) close up of “nodule” connections

Quilting Interconnect
The process flow for QP nodules is likely best inserted between the frontend- of-line (FEOL) and back-end-of-line (BEOL) process flows, similar to a "TSV-middle" approach. QP fabrication begins by patterning and etching voids or "pits" into what are normally the dicing streets. The pits are passivated, seeded, and filled by an electroplating process. CMP is then used to remove the metal overburden, similar to the damascene process. At this point, the rest of the BEOL is performed, with on chip interconnection and metallization fabricated. To singulate the die, a deep etch process can be used alone or in conjunction with a backside grind / polish step, analogous to the more well-known "dice before grind" approach. The nodule edges can then be coated with immersion tin or another solder material. The chips are aligned with applied pressure, and the tin is reflowed to solder together.
The process flow uses  industry‐standard tools and processes. It requires extra mask steps for nodule definition and chip separation.  After assembly, the completed “quilt” is handled as a “normal” chip.

Process Flow: (A) Nodules are embedded; (B) Interconnect is patterned; (C) Nodules are exposed and chips separated

IIC President Jason Kulick reports that “ Assembly and packaging of single die into multiple die "quilts" is  achieved with existing equipment, requiring little if any modification to pick-and-place and packaging tools.” After quilt assembly the packaging process can be completed as if the quilt were a single chip. There are multiple approaches to connecting die including soldering and laser welding.
Their interlocking nodule configuration allows for  sub‐micron chip‐to‐chip alignment which is highly sought after in several applications.


The extremely wide-bandwidth and low-loss RF/microwave performance of QP (< 0.1 dB insertion loss from 50 MHz past 100 GHz [4]) make it valuable to RF designers. Using quilting one can envision  “Monolithic” integration of GaAs, GaN, and other RF friendly IC materials with Si processor control. The possibility of directly interconnecting hetero circuits with Si and SiGe VLSI circuits opens up the possibilities for new system concepts, computer architecture and applications.

Large Format Arrays
Large format arrays appear to be an application that is highly suited for quilt packaging. Such arrays  suffer from yield issues associated with very large die. The costs for large imaging arrays and test arrays have become prohibitively expensive because of the wafer yields in fabricating readout integrated circuits (ROlC) and read in integrated circuits (RIIC). While attempts to alleviate this problem by tiling smaller, higher-yielding pieces together have been explored, these potential solutions typically result in less than ideal chip-to-chip spacing and alignment issues. By utilizing QP's unique characteristics, it is possible to create tiled arrays with sub-micron chip-to-chip alignment accuracy and seam gaps of ~ 10 um. In addition to alleviating the alignment and spacing issues, QP can also provide advantages by increasing I/O Count and reducing the negative effects induced from warping of whole wafers  or very large ICs. While hybridization of a pixel wafer to an IC wafer is very complex and  difficult, hybridizing to a tiled QP array will likely pose no additional problems, and may actually help with flatness issues. Large format arrays are currently a research focus for lIC and its industry partners.

IIC President Jason Kulick reports that “ ..From a reliability standpoint, Quilt Packaging has so far proven to be robust. While each application architecture and environment is different, QP in silicon and gallium arsenide has held up very well in thermal cycle and thermal shock testing”
IIC is currently working with Research Triangle Institute to develop a commercially viable process flow for transfer to their customers.

[1]  PE Garrou and I Turlik,” Multichip Module Technology Handbook”, McGraw Hill, 1998.
[2]. USP 7,612,443 (2009); 7,608,919 (2009); 8,021,965 (2011)
[[3] Interlocking nodule image courtesy Quanling Zheng, University of Notre Dame]
[4] Kopp, et al. Quilt Packaging of RF Systems with Ultrawide Bandwidths, Proc. 2009 IMAPS-RF Packaging Conference, San Diego, CA, September 2009



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