Fabricated on new 2-inch graphene wafers and operating at room temperature, the RF graphene transistors are said to beat the speeds of all but the fastest GaAs transistors, paving the way to commercialization of high-speed, carbon-based electronics.

"There are all kinds of extraordinary claims being made every day for graphene semiconductors, but this is the first demonstration of a RF graphene transistor that was made under technologically relevant conditions and scale," said IBM Fellow Phaedon Avouris, who oversees carbon-based materials efforts at IBM Research.

The graphene RF transistors were created for the Defense Advanced Research Project Agency under its Carbon Electronics for RF Applications (CERA) program. Almost four times faster than previous demonstrations, the graphene transistors were fabricated at the wafer scale using epitaxially grown graphene processing techniques that are compatible with those used to fabricate silicon transistors.

CERA's aim is to eventually build integrated graphene transistors to replace the discrete GaAs transistors currently used in military communications systems.

The two-inch graphene wafers were created by starting with commercially available silicon carbide (SiC) wafers, then burning off the silicon from the top layer in a process called thermal decomposition. The result was monolayers of graphene on the otherwise insulating substrate.

The graphene transistors were then patterned with a metal top-gate architecture that used high-k dielectric oxide insulated from the graphene layer by a polymer.

The graphene transistor is said to more than double the performance of silicon transistors of the same gate length (100GHz for graphene compared to 40GHz for silicon).

There are several relatively easy steps to further widen the gap between graphene and silicon. For instance, graphene suspended over an air gap and supercooled has achieve carrier mobilities of up to 200,000cm²/Vs compared to silicon's 1400cm²/Vs.

IBM's demonstration of room-temperature graphene on an insulating substrate only achieved 1500cm²/Vs.

The gate length of IBM's graphene transistor was 240nm, nearly 10x larger than the smallest gate lengths achievable with current lithographic techniques (under 35nm). By optimizing its process to increase mobility and shortening the gate length, IBM will next aim to increase the speed of its graphene transistor up to 1THz, which is the goal for the CERA program.