webleads-tracker

Home  >  ADVANCED PACKAGING  > 2.5 and 3DIC for those who can no longer afford scaling... ...
  >  ADVANCED PACKAGING
Jul 10th, 2014
 
2.5 and 3DIC for those who can no longer afford scaling... and not only
 
With continued scaling becoming difficult for the majority of companies to justify economically, the industry is looking to 2.5 / 3D integration to offer customization options till a replacement for CMOS can be implemented.
Send to a friend

Most in the industry are in agreement that scaling past the 22nm node, while still quite technically feasible, has priced itself out of most markets. With fab costs exceeding $6B, R&D costs exceeding $1.2B fewer and fewer IC houses will be able to put capacity in place at the next node. With design costs exceeding $150MM fewer and fewer products will have enough volume to absorb these rising NRE costs. 
 
Similar issues exist for the 450mm wafer program which was conceived to bring down the cost of the latest node ICs but has met with technical and economic cost issues of its own (notably in lithography).

3D integration is a system level architecture in which a chip is divided into a number of blocks or functions, each block is placed on a separate active layer  and these layers are  stacked and interconnected by vias directly formed through  the silicon or other semiconductor materials called a “through silicon via” (TSV). 
2.5 / 3D integration, or “More-than-Moore” as it is also known, through this stacking and interconnection of thinned IC layers proposes  to reach next node of electrical performance at what should be a more reasonable price , and with few technical hurdles to overcome. In addition, having shorter signal paths between die makes it possible to reduce the system's power consumption. 2.5/3DIC will offer an alternative to the economic constraints of scaling and will allow for functional combinations not currently feasible with standard SoC CMOS processing.

A 2.5D foundry flow is currently available from TSMC and soon will be offered by Global Foundries. 3D memory stacks, are being commercialized by Micron and Hynix and Samsung is expected soon.  All of the major design and test houses are onboard and the big 4 OSATS are all committed to assembly, packaging and test of such products.

While current 3DIC pricing is too high for commodity consumer products it has already penetrated the FPGA market and has been announced by Intel for high performance computing and by AMD and Nvidia for GPUs. Prices are expected to come down as volume grows.  

Amkor's roadmap for 2.5 /3D product introductions

Yole Développements latest “3DIC & 2.5D TSV Interconnect for Advanced Packaging - 2014 Business Update” will apprise the reader of the latest information on the status of 2.5/3D integration technology implementation and the state of the infrastructure.

 

 
More ADVANCED PACKAGING news

Sep 17th
Sep 11th
Sep 11th
Sep 11th
Sep 11th
 
©2007 Yole Developpement All rights reserved                  Disclaimer | Legal notice | To advertise
Yole Développement: Le Quartz, 75 cours Emile Zola, 69100 Villeurbanne, France. TEL: (33) 472 83 01 80 FAX: (33) 472 83 01 83 E-Mail: info @yole.fr