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Nov 28th, 2011
2.5D interposers: a closer look
Interest in silicon interposers, or “2.5D” as ASE’s Ho Ming Tong named them a few years ago, has certainly increased over the past few years and has culminated with the commercialization of the Xilinx Virtex-7. I-Micronews felt it was time to step back and take a “Closer Look”.
How do we define an interposer ? Traditionally the chip packaging community defines an interposer as the bridge between the on chip pitch and the on board pitch, i.e the interposer is traditionally the package. With 2.5D or 3D, once again it’s all about the pitch. Chip IO cannot be connected in a stack unless the interfaces have been standardized to match. Thus todays 2.5D interposer serves as a high density RDL so the chips can be connected either through the interposer, such as Elpida stacked memory [here] or next to each other on the interposer such as the Xilinx FPGA [here]. The latter structure bears a strong resemblance to the MCM-D of the 1990’s. The one criteria true for all of todays 2.5D interposers is that they must contain TSV.
Options for 2.5D Interposer Configurations: (left) Elpida memory stack); (right) Xilinx FPGA
The terms “active interposer” and “passive interposer” were coined by ST Micro a few years ago. The passive interposer is probably the one we are most familiar with, where the silicon interposer serves the function of RDL to reroute the chip IO for connection to each other, and position them for connection to the next level. The standard passive interposer is assembled in a BGA like package, such as the Xilinx Virtex-7 FPGA [here], but there are those that are proposing the Interposer can actually be the package and be directly assembled to the PWB (similar to a WLP) if constructed properly . The second classification is more controversial since the active interposer consists of a silicon chip containing TSV and circuitry. The example shown here is the recently announced Micron Hybrid memory cube [here] where the logic layer can be considered an active interposer. Many “3D purists” would simply consider this a 3D stack and you are likely to see it described both ways.
Active vs passive interposers
It is likely that 2.5D interposers will evolve in two density categories depending on their source of fabrication. The high density versions similar to what is being used by Xilinx will, by necessity, have to be manufactured by the foundries which have access to fine pitch dual damascene technologies , whereas the interposers with coarser features could be manufactured by the assembly houses using their RDL technology.
2.5D interposer categories based on ground rules
While all of the announced products have so far on silicon interposers there is significant R&D focusing on using glass, mainly due to the potential to reduce costs through its large format possibilities.
So who will be the source of interposers ? When looking at the supply chain, most believe that it will end up being some variation of the 3 options shown below (Foundry plus, OSAT plus or 3rd party) . The only interposer announcements so far are those of foundry player TSMC.
UMC, aligned with Elpida and Power Tech appears to be readying for the release of Elpida based memory products [here] and GlobalFoundries, which appears to be a little behind, has announced joint development programs and collaborations with the Fraunhofer, IMEC, IME and Sematech as well as potential partners and customers in the 2.5D/3D space [here, here] .
So far third parties such as EPWorks [here] have indicated that they can supply interposers, although in limited quantities, but no OSATS have announced that they intend to manufacture “coarse featured” interposers, but rather have been the ones looking for the suppliers.
Interposer supply chain options (Source: GlobalFoundries)
STATSChipPAC recently detailed their thoughts on 2.5D Interposer applications and listed logic + memory for GPU and gaming applications, logic + analog for network and telecom applications and the FPGA type applications as those that appear on the near horizon.
Interposer applications (Source: STATS ChipPAC)
We will certainly be keeping a close eye on the interposer space as it develops.
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