2014 VLSI Symposia programs have been published with a major image sensor news - Sony is to present its curved image sensor on the Technology Symposium. Both abstracts (Sony & TSMC) are presented below:
A Novel Curved CMOS Image Sensor Integrated with Imaging System
We realized an ultimately advanced imaging system that comprises a curved, back-illuminated CMOS image sensor (BIS) and integrated lens which doubles the sensitivity at the edge of the image circle and increases the sensitivity at the center of the image circle by a factor of 1.4 with one-fifth lower dark current than that of a planar BIS. Because the lens field curvature aberration was overcome in principle by the curved sensor itself, the curved BIS enables higher system sensitivity through design of a brighter lens with a smaller F number than is possible with a planar BIS. At the same time, we controlled the tensile stress of the BIS chip to produce a curved shape that widens the energy band-gap to obtain a lower dark current. The curved CIS can be applied to an ultimately advanced imaging system that is validated by the evolution of the animal eye in Nature.
Other big news is TSMC presenting its stacked sensor:
Advanced 1.1um Pixel CMOS Image Sensor with 3D Stacked Architecture
This paper demonstrates an advanced 1.1um pixel backside illuminated CMOS image sensor with a 3D stacked architecture. The carrier wafer in conventional BSI is replaced by ASIC wafer, which contains a part of periphery circuit and is connected to the sensor wafer through bonding technology. With proper layout design and process improvement, the impact of 3D connection (Through Via, TV) on the sensor performance can be significantly minimized. In addition, for the first time, the degradation of stacked pixel performance during the folded circuit operation under sensor array is found and improved. The final stacked sensor exhibits the comparable pixel performances to conventional BSI. Furthermore, stacked architecture provides the opportunity to enhance sensor performance by the separate process tuning for sensor wafers (without any effect on ASIC wafers), leading to a further improvement of dark performance.
To read more: http://www.vlsisymposium.org/program/