Intel recently commented that it is still exploring the future use of 3D devices based on through-silicon VIAs (TSVs), but that the company has still not found the right application or “product intercept” for the technology to justify the development and manufacturing costs. 

That comment drew my attention because, even with the growing interest among memory companies in TSV packaging techniques, Intel and some large memory companies share some common ground on this topic.

Somewhere along the path to high-volume production, something happens to the business plans of these large companies.  At some point, the challenge of constantly feeding those massive fabs begins to alter the product and business models. 

Most analysts can recount meetings or projects in which large companies have decided to abandon what appeared to be profitable opportunities primarily because that potential application did not consume enough wafer capacity to justify the effort. 

These instances are not examples of poor business practices, but rather are representative of a different dimension in the economies of scale for companies with exceptionally large manufacturing investments.  The challenge of keeping those fabs running at maximum capacity eventually begins to take on a larger role in determining short-term profit/loss and long-term product strategies—as can be easily demonstrated because memory companies have closed fully depreciated 200mm lines in an effort to balance cost/profit and supply/demand of DRAM and NAND.

I suspect this more complex investment strategy is the context that prompted Intel’s comment, and I believe that some large memory companies would also agree.  With few exceptions, movement toward 3D packaging can only be described as “tentative” among memory and logic companies holding numerous 300mm fabs.

The impact of 3-D packaging, however, on new and emerging memory technologies is profound. 

A financial strategy based on a relatively large number of identical wafers naturally leads to a product definition philosophy of “go big or go home.” This isn’t a very compelling message to potential investors who have already noticed the number of very large players who have opted to exit. 

The perpetual challenge for any emerging memory technology is the presentation of a realistic market entry point that will quickly lead to the kinds of manufacturing volumes capable of driving manufacturing costs down to the point of competing with NAND and DRAM.

The question is whether there is an alternative manufacturing strategy that doesn’t require very substantial case commitments from potential investors very early in the technology vetting process.

Advanced packaging technologies may not necessarily be the appropriate technology for enabling new high-volume applications that will substantially increase wafer demand for multi-core processors or for commodity products like DRAMs.  Such typical applications will likely still find better cost efficiencies with conventional printed circuit boards.

However, I believe that TSV and other 3D packaging technologies provide the manufacturing platform that supports a more controlled and gradual introduction of the new and emerging memory technologies. 

The conceptual shift is that the memory technology becomes enabled by the platform, not by a single high-volume application.

Advanced 3D packaging enables a richer platform of processors and controllers with a wider selection of high-performance, non-volatile memory, and with more flexibility in the interface between this product and real-world applications.  Rather than a single application such as the PC that propels a single memory technology into “winner-take-all” dominance, as was the case with DRAM, I anticipate that the conjunction of 3D packaging, single-core processors, and emerging memory technologies will be the platform that drives the wide range of non-volatile memory technologies into a number of applications.