Formed in late 2010, the SEMI 3DS-IC Committee recently approved its first Standard for publication during SEMICON West 2012. Pending successful procedural review, the Document will be published as SEMI 3D1, Terminology for Through Silicon Via Geometrical Metrology. SEMI 3D1 will provide a starting point for standardization of geometrical metrology for selected dimensions of through silicon vias (TSVs).
The Inspection & Metrology Task Force recognized the need for such a standard because although different technologies can measure various geometrical parameters of an individual TSV, or of an array of TSVs, such as pitch, top diameter, top area, depth, taper (or sidewall angle), bottom area, and bottom diameter, it is currently difficult to compare results from the various measurement technologies as parameters are often described by similar names, but actually represent different aspects of the TSV geometry. SEMI 3D1 is an important first step in promoting common understanding and precise communication between stakeholders in the 3D-IC manufacturing supply chain.
In addition, the 3DS-IC Committee is actively working on multiple other activities, organized within five task forces. The Thin Wafer Handling Task Force aims to develop standards for reliable handling and shipping of thin wafers and dies (e.g., micro-pillar grid arrays, or MPGA) used in high-volume manufacturing. As part of this effort the TF will define thin wafer handling requirements including physical interfaces used in 3D-IC manufacturing, as well as shipping requirements, including packaging, reliability, and other relevant criteria for both thin wafers and MPGAs. The task force’s first effort is SEMI Draft Document 5175, Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers. Current standards for shipping boxes, FOUPs, and FOSBs are not well-suited for the reliable storage and transportation of thin wafers and dice on tape frames used in 3D-IC manufacturing. Wafer thicknesses of 30-200um will need significant changes to the current design criteria of current wafer transport and storage containers. SEMI Draft Document 5175 aims to address the robust handling and shipping of thin wafers, including changes in securing the wafers (i.e., transportation/vibration and mechanical shock requirements).
The Bonded Wafer Stacks Task Force is nearing completion in its development of SEMI Draft Document 5173, Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack. Current wafer Standards (e.g., SEMI M1, Specification for Polished Single Crystal Silicon Wafers) do not adequately address the needs of wafers used in three-dimensional bonded wafer stacks for stacked integrated circuits. 3D-IC processes may require starting materials – silicon and glass wafers – with different tolerances for dimension and material than those specified in SEMI M1 and SEMI M24, Specification for Polished Monocrystalline Silicon Premium Wafers. Further, in each step of a 3D-IC process, the incoming material must be specified in terms of wafer dimension and materials present. Wafer thickness, edge bevel, notch, mass, bow/warp and diameters change when wafer stacks are bonded, debonded, and when wafers incorporated into stacks are thinned. Further, these parameters will change for a single wafer stack during process. This Document will provide the required properties of both silicon (“device”) wafers and glass (“carrier”) wafers to be used in 3D-IC applications. Templates for describing bonded wafer stacks and processed wafers to be used in the bonding flow would be provided as well. Also underway is SEMI Draft Document 5174, Specification for Identification and Marking for Bonded Wafer Stacks.
The Middle-End Task Force is looking at processes involving shared activities between wafer foundries and OSATs, including embedded via protrusion and viaed wafer thinning. Current work is focused on the middle-end process on wafers with or without TSVs, including post-final metal temporary bonding, wafer thinning, TSV formation and reveal, micro-bumping, redistributed line formation and carrier de-bond. The task force’s first two proposals are SEMI Draft Document 5473, Guide for Alignment Mark for 3DS-IC Process, and SEMI Draft Document 5474, Guide for CMP and Micro-bump Processes for Frontside TSV Integration.
The group that developed SEMI 3D1, the Inspection & Metrology Task Force, continues to develop Standards to be used in measuring the properties of TSVs, bonded wafer stacks, and dies used in 3D-IC manufacturing. Items under development include:
SEMI Draft Document 5270, Guide for Measuring Voids in Bonded Wafer Stacks, SEMI Draft Document 5409, Guide for Metrology for Measuring Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks, SEMI Draft Document 5410, Guide for Metrology Techniques to be used in Measurement of Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures, and SEMI Draft Document 5447, Terminology for Measured Geometrical Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures.
Lastly, the 3DS-IC Testing Task Force was chartered to develop Standards, Guides, and/or Specifications for electrical testing related activities used in 3D-IC manufacturing for the ultimate goal of yield enhancement, with future activities planned for design for test (DFT) such as test structures and placement; test methodologies such as contact method and test procedures; and test fixtures such as probe card and probe interfaces.
Ballots for the above activities will be issued throughout 2012, and are just the beginning of this global, industry-wide effort. Nearly 200 technologists from industry, research institutes, and academia around the world have already joined the SEMI 3DS-IC Standards Committee and are at work on these critical Standards. The committee and task forces will next be meeting in North America and Taiwan throughout the year. If your company is not yet involved, please register for Standards Program membership at: www.semi.org/standardsmembership