Home  >  ADVANCED PACKAGING  > 3D Integration Entering 2011...
Jan 31st, 2011
3D Integration Entering 2011
The performance and economic motivations for moving to 3D IC technology have been clear for several years.
Send to a friend

Motivation for 3D IC
The performance and economic motivations for moving to 3D IC technology have been clear for several years. By stacking one thinned die on top of another we achieve the shortest interconnect distances which results in less power required to drive a signal because the signal has less distance to travel. In addition entire layers of IP can be re-used, either through customization on a separate layer or by connection to other functions through an interposer.

Changing the current chip fabrication infrastructure  will surely not be a trivial or low cost undertaking. In fact Jeff Burns, director of VLSI systems at IBM/Yorktown Heights, has recently offered the perspective that 3D IC technology will require “…many changes to architecture, VLSI design, design IP, tools, technology, and manufacturing…. this promises to be much larger in scope than a CMOS technology generation -- rather, it will be similar to the transition from bipolar to CMOS" [1]. Still, most feel it is worthwhile when compared to projected costs for new fabs at 32 nm and beyond.  

Once the infrastructure is in place, it is hoped that 3D IC technology will reduce both risk and cost. The 3D IC approach should create economic benefits such as:  reducing the time it takes to design and verify chips at the most advanced nodes; allowing the use older analog IP blocks rather than having to develop new IP blocks at the most advanced process nodes and allowing the mixing of normally incompatible technologies (heterogeneous integration). 

As we enter 2011 activity continues at a frenzied pace but, customers looking to introduce  3D-IC TSV solutions into their next generation products are still encountering multiple challenges such as lack of standardization, unclear supply chain infrastructure, integration of package and testing, and the main obstacle - sourcing.  The commercialization bottleneck is the big foundries, TSMC, GlobalFoundries and UMC. The foundries are qualifying their top customers and qualifying  their internal 3D IC processes but have not released standard ground rules to everyone else at this point. Until the processes are qualified and the ground rules are fully released, the industry cannot fully engage. Once this is done, we will begin to see IP vendors develop for 3D and then we will see rapid growth.

Examining the foundry and OSAT roadmaps we see that commercialization is expected to begin now (2H 2011) and quickly develop in the 2011-2013 timeframe. The following table summarizes many of the recent commercial announcements.

Summary of recent announcements for 2,5D and 3DIC commercialization

Foundry Activities:
TSMC, at the recent IEEE IEDM conference in late 2010 TSMC announced that mass-production of 3D chips with TSV would start “..with the 28nm node within one to two years” [3]

In addition, TSMC has recently announced commercialization of silicon TSV interposers. This past fall Xilinx announced a single layer, multi chip silicon interposer for its 28nm 7 series FPGAs. Xilinx reported that chips would be fabbed by TSMC and assembled by Amkor [2].  By using TSV a silicon interposer, Xilinx reported that they  “.. reduced the risk involved with … full 3D IC stacking” . At the RTI ASIP 3D meeting in Dec 2010 Dr. Douglas Yu, Sr Director of the Interconnect and Packaging Division, indicated that TSMC “… will be offering commercial silicon interposers as we have recently announced with our customer Xilinx” [14]

To support 3D IC customer designs, TSMC has released TSMC Reference Flow 11.0 which enables 3D-IC integration to become part of the mainstream design flow. Both Cadence [15] and Synopsys [16] have contributed to these capabilities.

GLOBALFOUNDRIES senior vice president of technology Gregg Bartlett  announced a collaboration with Qualcomm and Fraunhofer IZM/ASSID in the summer of 2010 [17]. Bartlett indicated that “Until about 60nm progress was almost all about improving lithography….. Then a second driver came online, materials integration: strained silicon, HKMG. From 32nm onwards 3D integration is going to be a 3rd big driver, driving density higher”. Bartlett continued that they plan to support TSV 3D interconnect technology, with volume production expected to begin as early as 2013. “GlobalFoundries is currently developing a silicon interposer solution, putting an AMD CPU and a DDR3 DRAM on a substrate. The interposer solution will be followed by a vertical TSV technology, which GlobalFoundries will develop with its research alliance and OSAT  partners”. Bartlett added that “..the ability to support high-volumes of TSV-enabled ICs is a core focus of our technology roadmap” [5]. A few weeks ago, Globalfoundries CEO Douglas Grose announced that they plan to start offering “..3D stacking technologies including TSV  in or after 2011” [18].

The summer of  2010 also saw UMC announced a 3-way cooperation agreement with  Elpida Memory and  Powertech Technology (PTI) leveraging UMC's foundry logic technologies, Elpida's  DRAM technology and  PTI's assembly skills to develop a total 3D IC Logic + DRAM integrated solution. The total solution will include Logic + DRAM interface design, TSV formation, wafer thinning, testing and chip stacking assembly for customers. The resulting technology is expected to increase cost competitiveness, improve logic yield impact, and accelerate entry into the 3D IC market [4]. According to UMC CEO Shih-Wei Sun, they expect to start sampling integrated 3D IC solutions at the 28nm node in  mid-2011, with volume production slated for 2012. 

Memory Suppliers
Memory has always been viewed as the key application for this 3D TSV market whether it be stacked memory for miniaturization or wide I/O memory stacked on logic for access speeds.  In fact wide I/O interface memory for memory on logic applications has recently been called out as a key large volume driver for 3D IC technology [19]

                                 Nokia's wide I/O memory interface to Mobile CPU is expected to hit market by 2013

Samsung was the first memory supplier to show 3D IC  prototypes as early as 2006. In early 2009, Samsung showed prototypes of 8 Gb DDR3 with data rates of > 1600Mb/sec [24]. In late 2010 Samsung announced that they would begin mass production of 8GB DDR3 memory modules based on four-gigabit, 1.5V, 40 nm DDR3 memory chips operating at 1,333MHz and 3D TSV chip stacking technology. The new technology reportedly offers a 53% power savings when compared to two 4GB DDR3 modules. Samsung announced plans to apply this technology to 30nm-class and finer process nodes [7]. The modules will first see use in high performance servers where lower power consumption and increasing memory capacity are important. Adoption in Dell's Precision M6500 mobile workstationis expected starting in 2012 [13].

In the fall of 2009  Elpida announced the development of a similar 8-Gigabit SDRAM technology [“8 Gb 3D DDR3 DRAM using TSV Technology”, IEEE ISSCC, Feb. 2009, p. 130]. The 8-Gigabit, 1.3 mm high DDR3 SDRAM operated at 1,600Mbps and consists of eight 1-Gigabit DDR3 SDRAM chips and an interface chip. In the summer of 2010 they announced their partnership with  Powertech UMC [4] to develop memory on logic products. Elpida has recently indicated that the partnership was/is needed to satisfy infrastructure requirements, “…the partnership can take responsibility for the final stacked device …without the partnership, responsibility would be very difficult” [21].

Mark Durcan, COO of Micron, at the recent Semi  ISS meeting commented that Micron is currently ''sampling products based on TSVs” and that “mass production for TSV-based 3-D chips is slated in the next 12 - 18 months''[8].

Nanya Technology has announced a development program with  ITRI ( Industrial Technology Research Institute) to develop TSV technology for high-capacity DRAM products. Nanya expects to start shipping its integrated 3D solutions in small volume sometime in 2011 [9].

…the Equipment Suppliers Have Bought In
Traditional front end equipment suppliers have certainly bought into 3D Ic technology with both Applied Materials [22] and Novellus [23] having developed a suite of tools for manufacturing TSV and both heavily marketing their entry into this market space. 

…and Standardization is Underway
Since 3D IC technology requires new approaches to for semiconductor design, manufacturing, inspection, test and handling, a of industry convergence, or “standardization” must occur or we risk delaying industry success.
In 2010 JEDEC issued a publication  entitled “JEP – 158 Chip Stack with Through Silicon Vias: Identifying, Evaluating and Understanding Reliability Issues” and is currently working on a wide-IO memory standard which is  expected to  be completed in 2011.
SEMI (Semiconductor Equipment and Materials Industry association)  has recently formed a 3D Stacked Integrated Circuits (3DS-IC) Standards Committee to explore standardization.

Companies supporting the formation of a SEMI 3DS-IC Standards Committee include: Amkor, ASE, IMEC, ITRI, Olympus, Qualcomm, Semilab, Tokyo Electron, and Xilinx. Other companies involved in 3D IC standardization include GLOBALFOUNDRIES, HP, IBM, Intel, Samsung, and UMC.[24]

SEMATECH, the SIA (Semiconductor Industry Association) and SRC (Semiconductor Research Corp ) have established a 3D Enablement program to drive industry standardization efforts. The program, will focus primarily on developing technologies and specifications necessary for establishing standards in areas such as inspection, metrology, microbumping, bonding and thin wafer and die handling.  The program will be administered by SEMATECH’s 3D Interconnect program, based at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany [25].

The GSA (Global Semiconductor Alliance ) has announced a new 3D IC Initiative with a  goal of  helping to accelerate an industry-wide transition to 3D.  The initiative includes the formation of the 3D IC Working Group which  will include participants from  the major semiconductor companies, the supply chain including EDA, packaging and foundry [26].

Given the above, 2011 should prove to be a very active year on the road towards widespread adoption of 3D IC technology. Yole analysts will be keeping an eye out for future developments, all of which will be covered in detail in i-Micronews……………….


By Dr. Phil Garrou, Senior Analyst – Yole Developpement



Apr 17th
Apr 17th
Apr 9th
Apr 9th
Apr 9th
©2007 Yole Developpement All rights reserved                  Disclaimer | Legal notice | To advertise
Yole Développement: Le Quartz, 75 cours Emile Zola, 69100 Villeurbanne, France. TEL: (33) 472 83 01 80 FAX: (33) 472 83 01 83 E-Mail: info @yole.fr