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Apr 13th, 2012
 
3D-MAPS multicore processor: A closer look
 
3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM. In the last few months it has been described in detail at the IEEE ISSCC and the DAT- Europe conferences. I-Micronews thought it was worth “A Close Look”.
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The Georgia Tech team developing 3D-MAPS is led by Hsien-Hsien Lee (core and test), 3DIC veteran Gabriel Loh (data memory) and Sung Kyu Lim (CAD). This processor is designed to demonstrate the extreme memory bandwidth available using 3D interconnects.
3D-MAPS  contains 64 5-stage pipelined, 2-way in-order VLIW cores. Two dies are stacked in 3D-MAPS, one 64-core die and one SRAM die. Each core owns a dedicated 4KB SRAM tile, which is stacked above the core and connected using face-to-face 3D vias. 3D-MAPS demonstrates memory bandwidth of over 63 GB/s.

Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5×5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. Tezzaron  W TSV technology was used to stack two logic dies using face-to-face (F2F) bonding, where the top die is thinned to 12μm and the bottom die is 765μm thick.  These F2F pads are used for signal and P/G connections between the two dies. The diameter of a F2F bonding pad is 3.4μm, and their pitch is 5μm. 3D-MAPS uses 235 I/O cells that are placed along the periphery of the core die. Each I/O cell contains 204 redundant TSVs, where each TSV connects between a metal 1 landing pad and a backside metal landing pad deposited on the backside of the silicon substrate. Each backside metal landing pad (56×56μm2) is wire bonded to the packaging substrate. The diameter, height, and pitch of a TSV are 1.2μm, 6μm, and 5μm, respectively.

The 3D-MAPS processor is fabricated using a Global Foundries six-metal 130nm process modified to include Tezzaron TSVs.  TSVs are etched into the silicon and filled with Tungsten. Then devices and metal layers are patterned. Next, wafers are flipped and bonded. Finally, one wafer is thinned until the trenched TSVs are revealed from the backside. This produces a two-layer face-to-face bonded stack that uses TSVs for IO. Because the wafers are bonded before thinning, there is never a need to handle a thinned wafer. With metal layers, the thinned die is 12μm thick and the thick die is 765μm.

TSVs are approximately 1.2μm wide with 2.5μm minimum pitch and 6μm height. The face-to-face (F2F) connection, which is used for the main die-to-die communication, uses 3.4μm Metal 6 pads with 5μm pitch. The TSVs have a parasitic resistance of around 600m  and a parasitic capacitance of about 15fF. The F2F connection has negligible resistance and capacitance. The 3DMAPS die footprint is 5×5mm thus the max face-to-face connection count is one million. The physical design summary is shown in the table.

(A) Core and memory layers; (B) Cross section of the processor/memory die stack (C) Die stack in Amkor package
 


Physical Design Summary for 3D-MAPS

Their  tool-flow is based on commercial tools from Cadence, Mentor Graphics, and Synopsys and enhanced with various add-ons they developed to handle TSVs and 3D stacking.

3D MAPS version 2 s already been designed and taped out. It will have 5 layers and a wide IO interface. It is shown schematically below with proposed specs compared to 3D MAPS 1 .

 
3D MAPS V2; (A) functions of the 5 tiers; (B) Comparison to 3D MAPS V1

 

 
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