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Feb 27th, 2012
 
3D processor - memory mashups take center stage
 
Here is a great article by Rik Myslewski posted on February 24th from ISSCC, San Francisco, giving an overview on 3D stack prototypes presented during the conference.
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A trio of devices that stack layers of compute units and memory in a single chip to boost interconnect bandwidth were presented at this week's International Solid-State Circuits Conference in San Francisco.

Sharing the stage at the ISSCC's High Performance Digital session were three technologies; one prototype developed by IBM that places cache memory layers on top of a "processor proxy" layer, and two working chips – one developed at the University of Michigan, and another by the Georgia Institute of Technology working with KAIST and Amkor Technology, both in South Korea.

Note that these parts aren't merely RAM-stacked-on-top-of-a-processor packages such as, for example, Apple's A5. These are single parts with processor and memory closely coupled, married together in a single slab.

The ISSCC presentations each were titled in impressive boffin-speak – so impressive that we'll quote the title of each paper before we dig into a few of its details.

IBM's TSVs are connected layer-by-layer with tiny conductive balls.

IBM's "3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias": Like the other two chips, the IBM prototype routes data, clock, and power signals through its layers – what IBM calls "strata" – by means of through-silicon vias (TSVs).

TSVs are essentaily just what they sound like: signal paths that are etched through a silicon layer and filled with a conductor. In IBM's prototype, the TSVs are copper-filled, and are about 20 micrometers (0.0008 inches) in diameter.

Full text here.


 
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