Backgrinding, which is used in nearly all 3D wafer thinning processes, is known to generate residual stress in the silicon and a layer of damage (crystalline defects and microcracks). Additional processes such as CMP, dry etch etc. are carried out after backgrinding to release the residual stress and minimize the damage layer.

At the recent IEEE 3DIC conference in Japan, AIST (Advanced Industrial Science and Technology lab – Tsukuba) reported on their comparison of wet chemical etching to other final thinning options. I-Micronews thought it was worth “A Closer Look”.

200 mm SI wafers were thinned by spin etching with HF/HNO3 solutions, water rinsing and drying. Surface damage was measured by die fracture stress measurements and then electrical measurements were made to measure the impact of the various thinning options on MOSFET characteristics. 

Weibul plots for the die fracture stress for the various thinning methods are shown below. Backgrinding  only shows the worst fracture resistance and fully wet etched wafers show the best as expected. At 50% probability, backgrind + CMP and backgrind + 10 um wet etch were ~ equal. 

Weibul plots for die fracture stress

Wafer thinning to 100 and  50 um and subsequent measurement of MOSFET characteristics of threshold voltage, V th ; , g ; and off leakage current, Ioff  were evaluated. Changes were very small even when the wafers were thinned down to 50 um. Changes were 20 mV, 3.5% and 6 pA respectively indicating that wet etching  has a small impact on such electrical characteristics.
 

Histograms of change in MOSFET characteristics after thinning

From this data one can conclude that backgrind + wet etch can be a viable alternative to backgrind + CMP.