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> ADVANCED PACKAGING: 3D IC, WLP & TSV
Aug 16th, 2010
ASET Consortium Update at Semicon 2010
3D IC veretan Mitsumasa Koyanagi of Tohoku University gave an update on Japan's "Dream Chip" project at the recent Sematech "Stress Management for 3D ICs ..." workshop at Semicon 2010.
Japan has been funding 3D IC R&D since the inception of the first ASET project in 1999. The current Dream Chip project started in 1998. Research funding for 2009/2010 is 3.4 billion yen. 17 companies (shown below) are providing 97 researchers to work on this program.
Dream Chip program goals include:
Potential Dream Chip application areas include healthcare, advanced consumer electronics, automobile auto-pilot and high speed communications. The ASET roadamp shows stacked DRAM in 2012-2013 and 3D applied to high speed communication devices and high performance image processing device a few years later. The first demonstration device (below) is memory on logic mated on a Si TSV interposer which is scheduled for delivery in 2012. The second demonstration device will be a high speed image processing system. Requirements for this device include:
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