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Aug 16th, 2010
 
ASET Consortium Update at Semicon 2010
 
3D IC veretan Mitsumasa Koyanagi of Tohoku University gave an update on Japan's "Dream Chip" project at the recent Sematech "Stress Management for 3D ICs ..." workshop at Semicon 2010.
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Japan has been funding 3D IC R&D since the inception of the first ASET project in 1999. The current Dream Chip project started in 1998. Research funding for 2009/2010 is 3.4 billion yen. 17 companies (shown below) are providing 97 researchers to work on this program.

  • Device Manufacturers: Elpida, Toshiba, Renesas, Rohm
  • Electronics Equipment Manufacturers: Fujitsu, Hitachi, IBM Japan, NEC, Panasonic, Sharp, NAC Image Technology
  • Materials & System Manufacturers: Advantest, Ibiden, Shinko, Tokyo Electron, Toppan Printing, Yamaichi Electronics

Dream Chip program goals include:

  • Design environment technology
  • Interposer technology
  • Chip test technology
  • Cooling & stacking/bonding technology
  • Thin wafer technology
  • Demonstration devices - design & development
  • Architecture and design technology for reconfigurable devices
  • 3D integration technology for reconfigurable devices
  • Multi-band variable RF MEMS device technology
  • Multi-band communication front end circuit

Potential Dream Chip application areas include healthcare, advanced consumer electronics, automobile auto-pilot and high speed communications.

 
Dream Chip application areas
Dream Chip application areas

  

 
ASET roadmap
ASET roadmap

The ASET roadamp shows stacked DRAM in 2012-2013 and 3D applied to high speed communication devices and high performance image processing device a few years later. The first demonstration device (below) is memory on logic mated on a Si TSV interposer which is scheduled for delivery in 2012.

 
Memory on logic on Si interposer
Memory on logic on Si interposer

   

 
High speed image processing system
High speed image processing system

The second demonstration device  will be a high speed image processing system. Requirements for this device include:

  • Ultra high speed image data output (more than 10,000 frames/sec)
  • Multiple parallel one screen (frame) image process
  • High speed pipeline process within image process block from image sensor layer to procesor calculation circuitry layer

 
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