The concept model test cell dubbed, DIMENSION, integrates a high parallel test cluster along with singulated die and 3D die stack automated handling capabilities. At the ADVANTEST EXPO 2012 taking place on June 6-7 at the Tokyo International Forum, Advantest will display the concept test cell solution for die handling, test, and production line integration. From wafer to Known Good Die (KGD) and Known Good Stack (KGS), the DIMENSION concept shows the direction of 2.5D and 3D production-capacity, specification performance, and superb yield
                              
Enabling 2.5D and Partial Stack                              
2.5D- and 3D-stack technologies offer outstanding improvements to density, power and performance. The primary concerns of this emerging architecture are 1. Delicate and thin die handling, 2. Active thermal management, and 3. Overall yield management. The DIMENSION concept addresses these issues with SmartDieCarrier (SmtDCTM) technology. SmtDCTM solutions provide die pick & place plus very fine pitch contact with both extreme precision and delicate soft touch handling. And Active Thermal Control (ATC) with real time power management achieves yield and specification compliance. Adding confident yield to the 3D equation the Dimension concept enables stacked device commodity.
                              
Wide I/O DRAM                              
True TSV 3D applications deliver outstanding performance with superb power reduction and physical density benefits. The JEDEC Wide I/O Mobile DRAM provides 8X the bandwidth with 1/4 to 1/2 the I/O power of conventional DRAM architectures. But today's market also demands highest yields with commodity class economy. Wide I/O DRAM and future 3D TSV heterogeneous devices will depend on KGS and superb productivity. The DIMENSION concept demonstrates KGD and KGS solutions for smart phones and tablets of tomorrow as well as the telecom routers and super computing CPUs now under development.