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Mar 22nd, 2012
Altera and TSMC develop heterogeneous 3DIC test vehicle with 2.5D Interposer
Altera Corporation and TSMC today announced the joint development of the world’s first heterogeneous 3D IC test vehicle using TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process.
Heterogeneous 3D ICs are one of the innovations enabling the industry’s move beyond Moore’s Law by stacking various technologies within a single device, including analog, logic and memory. TSMC’s integrated CoWoS process provides semiconductor companies developing 3D ICs an end-to-end solution that includes the front-end manufacturing process as well as back-end assembly and test solutions.
Altera is the first semiconductor company to develop and complete characterization of a heterogeneous test vehicle using TSMC’s CoWoS process. This and additional test vehicles enable Altera to quickly test the capabilities and reliability of 3D ICs to ensure they meet yield and performance targets. TSMC’s CoWoS process combined with Altera’s technology leadership in silicon and intellectual property (IP) lays the foundation for rapid and cost-effective 3D IC product development and deployment in the future.
Altera 3D SiP with Silicon Interposer (Courtesy of Altera)
Altera’s vision for heterogeneous 3D ICs includes developing device derivatives that allow customers to mix and match silicon IP based on their application requirements. Altera will leverage its leadership position in FPGA technology and integrate various technologies with an FPGA, including CPUs, ASICs, ASSPs, memory and optics. Altera’s 3D ICs enable customers to differentiate their applications by leveraging the flexibility of the FPGA, while maximizing system performance, minimizing system power and reducing form factor and system cost.
“Our partnerships with standards bodies like IMEC and SEMATECH, and our use of TSMC’s leading-edge CoWoS manufacturing and assembly process put us in an excellent position to execute on our strategy of delivering heterogeneous 3D devices to our customers at the right time and with the right set of features,” said Bill Hata, senior vice president of worldwide operations and engineering at Altera. “Implementing heterogeneous 3D capabilities into our devices enables us to continue our path of technology innovation and leadership, and carry us beyond Moore’s Law.”
“Our relationship with Altera dates back nearly two decades, and in that time we have worked closely together to develop the most leading-edge manufacturing processes and semiconductor technologies,” said Rick Cassidy, President of TSMC North America. “Developing next-generation 3D ICs with Altera is a good example of how the two companies can work together to push semiconductor technology to another level.”
CoWoS is an integrated process technology that attaches device silicon chips to a wafer through a chip on wafer (CoW) bonding process. The CoW chip is attached to the substrate (CoW-On-Substrate) to form the final component. By attaching the device silicon to the original thick wafer silicon before it finishes the fabrication process, manufacturing-induced warping is avoided. TSMC plans to offer CoWoS as a turnkey manufacturing service.
Schematic cross section of Altera 3D SiP (Courtesy of Altera)
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