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May 15th, 2013
Analysis of TSV proximity effects in planar MOSFETs and FinFETs
The impact of TSV-induced stresses on transistor performance are simulated, and a "keep-out-zone" is identified.
Over the last several years, the semiconductor industry has made significant strides in demonstrating the technical feasibility of 3D-IC integration in several different configurations, each with its own challenges and potential benefits. For example, memory cubes comprised of stacks of NAND FLASH or DRAM memory die, connected internally with through-silicon vias (TSVs), have already been manufactured by several companies. Memory cubes reduce the form factor of the memory product and improve performance because of shorter electrical interconnections. In another configuration, silicon interposer technology, also known as 2.5D-IC, mitigates a number of challenges that arise in die-stacked 3D-IC, while offering the advantage of shorter inter-die connections relative to traditional 2D packaging. The silicon interposer approach is expected to evolve into more complex and higher value implementations by moving the I/Os and the global power and ground mesh onto the interposer. However, silicon interposer technology does not offer the full benefits of form factor reduction and electrical performance advantages envisaged with die-stacked 3D-ICs, which provides the motivation for the industry to continue the research and development needed to overcome the technical and commercial barriers toward the commercialization of die-stacked 3D-ICs.
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