Home  >  ADVANCED PACKAGING  > Analysis of TSV proximity effects in planar MOSFETs and Fin...
May 15th, 2013
Analysis of TSV proximity effects in planar MOSFETs and FinFETs
The impact of TSV-induced stresses on transistor performance are simulated, and a "keep-out-zone" is identified.
Send to a friend

Over the last several years, the semiconductor industry has made significant strides in demonstrating the technical feasibility of 3D-IC integration in several different configurations, each with its own challenges and potential benefits. For example, memory cubes comprised of stacks of NAND FLASH or DRAM memory die, connected internally with through-silicon vias (TSVs), have already been manufactured by several companies. Memory cubes reduce the form factor of the memory product and improve performance because of shorter electrical interconnections. In another configuration, silicon interposer technology, also known as 2.5D-IC, mitigates a number of challenges that arise in die-stacked 3D-IC, while offering the advantage of shorter inter-die connections relative to traditional 2D packaging. The silicon interposer approach is expected to evolve into more complex and higher value implementations by moving the I/Os and the global power and ground mesh onto the interposer. However, silicon interposer technology does not offer the full benefits of form factor reduction and electrical performance advantages envisaged with die-stacked 3D-ICs, which provides the motivation for the industry to continue the research and development needed to overcome the technical and commercial barriers toward the commercialization of die-stacked 3D-ICs.

From the point of view of process development and transistor performance, the fabrication and integration of the TSVs within a 3D-IC system presents a number of challenges. These challenges, though manageable, need to be taken into account. Copper is the material of choice for the via conductor, due to its excellent electrical conductivity and pervasiveness in modern interconnect stacks. However, copper and silicon have very different coefficients of thermal expansion. Since the TSV fabrication steps involve thermal operations, the thermal mismatch of these materials induces stresses in the silicon surrounding the TSV. These stresses in turn alter the carrier mobility and on-current of the transistors fabricated in the proximity of the TSV, through the same piezoelectric effect in silicon which is responsible for boosting the transistor performance in strained-silicon technologies. This so-called TSV stress proximity effect has a range of several microns and can either produce enhancement or degradation of the current. In addition to the TSVs, the micro bumps used for inter-die connections and the solder bumps, used to attach the die stack to the bumps, also induce stresses in their proximity. Besides their impact on transistor performance, these induced stresses lead to structural reliability concerns such as cracking and delamination.

By Ricardo Borges, Victor Moroz and Xiaopeng Xu, Synopsys, Mountain View, CA.

To read more: http://www.electroiq.com/articles/sst/print/volume-56/issue-3/features/packaging/analysis-of-tsv-proximity-effects.html?cmpid=EnlAPMay132013


Sep 17th
Sep 11th
Sep 11th
Sep 11th
Sep 11th
©2007 Yole Developpement All rights reserved                  Disclaimer | Legal notice | To advertise
Yole Développement: Le Quartz, 75 cours Emile Zola, 69100 Villeurbanne, France. TEL: (33) 472 83 01 80 FAX: (33) 472 83 01 83 E-Mail: info @yole.fr