Since 2009 when Jack Sun, VP of R&D, announced that  TSMC  would be  constructing a 300 mm 3DIC line at Fab 12 in Hsinchu which would be ready for commercial production “..within 2-3 years” we have been awaiting the major product announcement that would finally put 3DIC on the map. 

In late 2011 TSMC announced that they had begun shipping samples based on their 2.5D technology called CoWoS (chip on wafer on substrate), to customers and were expecting small volume production in 2013 and mass production in 2014 [here]. Dr Jack Sun, TSMC on the right.

At the fall 2011 Global Interposer Technology Conference at Ga. Tech., Doug Yu, Sr R&D Director at TSMC, indicated that they planned on manufacturing both the chips and the interposers (including the bumping) so that “…there is clear ownership and an efficient route to cost and yield improvements” . TSMC claims its approach will be “…simpler, cheaper and more reliable than using multiple foundries, packaging houses and other partners” Their "first generation " 3D customers (such as Xilinx) will be able to continue using external packaging partnerships if they choose (such as Amkor). However, when the 3DIC assembly service is offered for general consumption in early 2013 TSMC plans that for most customers the assembly and test will be done by TSMC. [here].

Known 2.5/3D customer programs currently include Xilinx, AMD, Nvidia, Qualcomm, TI, Marvell and Alterra.

This spring, at the TSMC technology symposium, we saw major moves into the realm of advanced packaging with offerings such as bumping and chip scale packaging with eutectic bump, leadframe bump, wafer level CSP, bump-on-trace, silicon interposer and fan out WLP either being offered or in development [here]. This appears to be a calculated move to gain a strong foothold in the IC packaging market. 

TSMC advanced packaging offerings

For instance, CENS reports that TSMC is staffing their 2.5/3D program with more than 400 specialists  many of which they are recruiting away  from Taiwan’s IC assembly houses such as ASE, SIliconware and Powertech [here].

3DIC and CoWoS appear fairly well entrenched in the 2012  TSMC roadmap. TSMC reiterated that only the memory and the package substrate need come from outside, with TSMC taking the packaged chips through final test, once a stronghold of the OSAT community in Taiwan.

TSMC proposed manufacturing flow for chip-on-wafer-on-substrate ( 2.5D)

Interposers and bump technologies will be available from both the Hsinchu and Tainan sites.
On May 31st, 2012 Xilinx became the first production product fabricated using TSMC 2.5D silicon interposer technology when they announced shipment of the Virtex®-7 H580T FPGA [here].  In early 2012 Altera and TSMC announced a similar FPGA development program [here]. However, FPGAs, although a significant technical accomplishment, are not the major HVM product announcement that we have all been waiting for. 

The big product announcement could be the A6 processor which is expected to be used by Apple in the iPhone 5 and the iPad 4. Rumors about the A6 processor are scattered and contradictory, but most sources report that due to the legal battle between Apple and Samsung, over Galaxy smartphones and tablets, it is quite unlikely that Apple will continue with Samsung as its manufacturer, but rather TSMC is likely to become the manufacturer of choice for the A6 [here].

Apple A6 Processor

If the prevailing rumors are correct, the A6 will be a quad-core Cortex-A9 built with 28nm technology and 2.5D architecture .
Last summer the rumors were rampant that TSMC was in trial production ahead of a launch expected in 2012. TSMC was rumored to be testing its 28nm processes and 2.5D stacking technology on the A6 with Apple. TSMC and Apple publically declined  comment on such speculation [here].

Last fall, Digitimes reported that the two companies had  signed a foundry partnership agreement, for  the  A6 chipset and its successor the Apple A7 to be produced using TSMC’s 28nm and 20nm processes and TSMCs stacked 2.5D process, but again no announcement from Apple or TSMC [here].

There have been rumors in the past suggesting that TSMC lost the chance for making Apple A3 processors to Samsung because it had no capability to package and test the chips. This recent major move into advanced packaging and full 2.5/3D component design /manufacturing  and test may be an attempt to insure that  this does not happen again.

Hopefully Apple’s assessment of the readiness of TSMCs 28 nm and CoWoS technologies was positive and we will be seeing an announcement from the two major players soon.