As the industry has lowered its chip-testing costs over the years, IC test has been predictable and somewhat dull. But in the emerging 2.5D and 3D chip era, IC test is entering the spotlight and the traditional test flow is under the gun.

In some circles, test is the biggest challenge to enable the 2.5D/3D chip era. The bottom line is that the industry must keep 2.5D/3D test costs at bay — or the technology won’t fly. “Test is going to be a huge challenge,” said Ivor Barber, director of packaging technology at LSI Corp., at a recent 3D chip panel. “Known-good-die (KGD) is also a real challenge.”

It seems like déjà vu, but the age-old problem of testing a key component in 2.5D and 3D designs — KGD — has resurfaced again. Steve Pateras, product marketing director for Silicon Test Systems at Mentor Graphics Corp., said the industry will also require “new techniques” to test the silicon interposers, through-silicon-vias (TSVs), not to mention the 2.5D/3D chip designs themselves.

And in another critical piece of the test puzzle, there is a little-known debate brewing over a 3D design-for-manufacturing (DFM) standard. Within the IEEE, a relatively new entity — the 3D-Test Working Group — is hammering out a proposed standard called IEEE 1838. The proposed standard hopes to define the architecture and description language for the “test access” point within a 3D device. A test access point is critical, because it can be used to test and ensure the quality of a 3D device during the IC flow.

Now, the group is looking at two possible and rival test access technologies: One is based on the IEEE 1149.1 boundary scan standard, while the other is built around the IEEE 1500 embedded core architecture scheme. It is unlikely that the group will endorse both technologies. “For the moment, I think it’s preferable to have one standard,” said Erik Jan Marinissen, principal scientist at IMEC and chairman of the 3D-Test Working Group.

Full article here: http://semimd.com/blog/2011/12/12/test-challenges-and-dfm-debate-seen-in-3d/