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Jan 27th, 2012
Discussion about wide IO memory and high-performance DRAM stack design
Here is an interesting article from “EDA360 Insider” about high-performance DRAM memory stack design and recent major announcements on wide IO memory chips.
For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might get. I started thinking about the year’s major announcements and here’s my short list:
I then started to think about designing my own version of the Micron/IBM HMC using standard Wide I/O memory chips instead of the specialized memory chips Micron has developed for the HMC. Those Micron memories incorporate 16 memory arrays—each with a separate I/O channel—onto each die. The HMC can therefore deliver a peak throughput of approximately 160 Gbytes/sec. It’s designed for high-performance computing applications, which is why IBM is interested in the technology.
In contrast, a Wide I/O SDRAM is designed for low-power and mobile applications with somewhat less performance. One Wide I/O SDRAM delivers about 17 Gbytes/sec of bandwidth through four memory arrays and four 128-bit interface ports. Not shabby compared to DDR memory DIMMs, but not HMC-class performance either.
Because I expect Wide I/O memory parts to go into high-volume production over the next couple of years due to the demand of mobile designs, I decided a thought experiment using these parts was in order to round out the year. So let me take you on my quick flight of fancy through a top-level conceptual design to see where this technology takes us.
First, I plan to use stock Wide I/O memories, which gives me 17 Gbytes/sec peak bandwidth from each Wide I/O memory chip (or memory stack, because I can stack as many as four Wide I/O die using 3D assembly techniques to get additional memory capacity but I get no additional memory bandwidth by stacking Wide I/O die). Four such memories or memory stacks will deliver about 68 Gbytes/sec of memory bandwidth—somewhat less than the HMC, but close enough for a thought experiment and plenty of bandwidth to make the experiment interesting.
Full article here.
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