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Nov 7th, 2012
Embedded wafer-level-package activity is expected to pick-up by 2015 above $200M, says Yole Développement
FOWLP & Embedded Die Packages, a report from Yole Développement now available.
Yole Développement announces its FOWLP & Embedded Die Packages report. In this report, Yole Développement offers an analysis of both FOWLP and Embedded die package technologies detailing key market drivers, benefits and challenges application by application, technology roadmaps and manufacturing tool-box, supply chain perspectives, key players and emerging infrastructure for Embedded WLP. A package cost structure analysis based on real products available on the market completes the analysis.
FOWLP technology is looking for new driving forces beyond Intel mobile’s push
Low reliability on large package body size and lack of flexibility in the IC to package co-design process are the two main factors limiting the wide adoption of FOWLP technology on the wireless IC market. Indeed, FOWLP technology imposes a specific redesign of the chip for efficient integration into the package: both Infineon and STEricsson (who already have products on the market) spent almost 18 month to redesign their baseband and RF-Transceiver SoCs in order to place the pads at optimized locations and match with a single RDL, 0.5mm board pitch eWLB package design. FOWLP is a restrictive package technology for most of the world’s IC designers to adopt efficiently, especially fabless chip companies. This is why only big semiconductor IDM companies having IC-to-package co-design environments well established in-house can drive and support the initial growth of this new wafer-level-packaging platform at its early stages.
Two main OSATs supporting FOWLP infrastructure today. Four more players to come next!
NANIUM (PT) and STATS ChipPAC (SG) shared more than 80% of the $107M FOWLP activity revenue last year, mainly driven by Intel Mobile’s volume demand on eWLB production. While ASE (TW) is shutting down its 200mm eWLB operations this year to focus on future generation FOWLP technologies, many OSAT players are presently in qualification phase such as ADL (TW), Amkor (KR) and NEPES (SG). Additional packaging houses are expected to come onboard in the 2013 – 2014 time frame such as TSMC (TW), SPIL (TW) and J-Devices (JP). More details on the supply chain challenge and the partnership already in place are provided in this research report update.
Embedded die package platform successfully entered the SiP module business
The most pragmatic approach to commercialize embedded die package technology will be to initially start with simple, low cost, low I/Os, small die analog & power IC applications (such as DC/DC converter modules, IPD networks, RFID, Power MOSFET, IGBT modules, auto-focus driver ICs, etc…).
Embedded die packaging is supported by a game changing, low cost, panel area, PCB based infrastructure that has the potential to create a new space, an alternative supply chain for today’s well established package standards such as QFN/SOT/WLCSP/BGA platforms. Being intrinsically “3D” capable, the technology is well positioned to meet the future requirements of miniaturized, low cost 3D SiP module configurations.
“Today, first generations of FOWLP and embedded die package technologies are not really competing as they are driven by different players and will initially target very different application spaces. However, this situation is likely to change radically in the near future as “2nd generation” derivatives of both platforms appear on the market,” adds Jérôme Baron, Business Unit Manager, Advanced Packaging at Yole Développement.
More information about the report here.
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