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Jan 23rd, 2013
The Evolution of memory integration: a closer look
At the recent IEEE IEDM meeting in Dec 2012 Subramanian Iyer of IBM Systems and Technology group explained the evolution of high end memory + logic systems. iMicronews thought it was worth … A Closer Look.
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At the recent IEEE IEDM meeting in Dec 2012 Subramanian Iyer of IBM Systems and Technology group explained the evolution of high end memory + logic systems. iMicronews thought it was worth … A Closer Look.

Fig. 1 shows the evolution of embedded memory configurations. At each step along the way, there are significant improvements in overall system power as well as system performance and latency. 

 Figure 1 The Evolution of Memory Integration

First, the standalone SRAM L3 cache was replaced with eDRAM caches on a ceramic (and later organic) multi-chip module (interposer). The embedded DRAM provided about 4X improvement in memory density, a 5-8X reduction in memory power, and a >1000X improvement in soft error rates compared to SRAM.

At 45 nm when the latencies on the MCM became significant compared to processor clock frequency, cache memory latencies could no longer be sustained by an MCM solution and the eDRAM had to be integrated in the same SOI technology used for the processors. This was the very first SOI DRAM (embedded or otherwise).

With the wider utilization of multicore processors and the need for even larger amounts of  cache, cache-processor stacks are expected to proliferate. Fig. 2 and 3 show 3D integrated eDRAM die. The aspect ratio of the TSV in the thinned die is <10:1. The key considerations for TSVs are where one integrates them in a hierarchical backend interconnect scheme. IBM chose to integrate the TSVs at the “fat” wire levels for two reasons: as chip-to-chip interconnects, the higher levels of the hierarchy are appropriate, and to minimize the dimensional incongruity of TSVs (several microns across) with respect to a contact dimension of a few tens of nm.

The copper TSVs reportedly present several challenges, including the large CTE difference. Control of the Cu microstructure reportedly minimizes the deleterious effects of this large mismatch.

Die may be attached both face to face, or face to back which  allows for multi die stacking. The stacking process is very sensitive to die warpage and the handling of thin die and controlling their warpage is reportedly a key challenges.

Fig 2 Fully Packaged, Fully Functional eDRAM on a Logic face-to-face Die Stack on Organic Laminate fabricated in IBMs 32nm process

Fig. 3  A Close up SEM of the Thinned Lower Die Showing Interconnect Layers, TSV and deep trench caps. 

Finally the integration of 3Di main memory with multiple processor-cache stacks on a silicon interposer will allow the potential to provide board level integration.
Si interposers are today’s MCMs. The ability to integrate silicon-like BEOL technology on the interposer allows very high bandwidth between die. Fig. 4 shows the integration of a 45 nm SOIbased processor with eDRAM, with two SiGe BiCMOS transceiver chips. The bandwidth between chips exceeds 2Tb/s, far greater than achievable by either ceramic or organic interposers. Silicon interposer technology can also include decoupling capacitors for mid frequency power supply noise reduction.

Fig 4 Heterogeneous Integration of two SiGe BiCMOS die with a 45nm Cu ASIC with eDRAM on a silicon interposer. In spite of larger intrinsic losses compared to ceramic and organic interposers, the tighter interconnect pitches and distances allow for an inter die bandwidth >2Tb/s.

Iyer concludes that “As scaling saturates, and lithography sputters to a grinding halt, these orthogonal scaling techniques will assume even more importance and continue to keep Moore’s law alive”.



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