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May 22nd, 2014
GE POL embedded packaging platform: a closer look
Embedded electronic packaging technologies have seen significant growth due to their ability to reduce the size and cost of components and enable higher levels of integration for feature-rich consumer products such as smartphones and tablets.
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GE an early adopter of embedded packaging
GE was one of the earliest adopters of embedded technology with their internally developed “Chips First” technology in the early 1990’s [1]. Over the years, this was developed as a high frequency, power packaging solution known as “Power Overlay” (POL) technology.
Miniaturization, improved electrical and thermal performance and enhanced reliability have been the primary drivers for component embedding within GE for advanced power conversion in aviation and energy management application spaces, and other applications. 

A POL multichip example of an SMT power module

The POL platform can also meet the price points required for consumer products. This process starts with the lamination of a polyimide (PI) film to a metal frame. The film is coated with a thermoset adhesive. Die are mounted face down and vias are formed from the reverse side by laser ablating the PI film and adhesive. Subsequent via filling, copper patterning and package molding is by standard technologies.   The process is currently run on a 9 inch frame and the technology is reportedly adaptable to panel size processing.

GE POL process flow for low cost consumer packaging

GE expands their embedded technology base
In 2013 GE acquired Imbera Electronics Oy, which had spent more than 10 years developing advanced PCB embedded electronics packaging technology and manufacturing solutions. One of the Imbera PCB based process flows is shown below. The IMB core is manufactured in the same way as a normal PCB core, using standard materials. Pressing is performed using a standard HDI multilayer vacuum press that produces a very planar and void free structure. Embedded components don’t experience undue pressure during the pressing process.

Typical Imbera PCB based embedded die process flow

Below there are some of the package types available by using the “POL” platform. 

Package configurations possible by GE’s POL technology

Cost is key
For any technology to be adopted in high volume manufacturing the economics must be right. Risto Tuominen, former CEO of Imbera Electronics Oy, points out that POL technology has some unique capabilities that differentiate it from other available embedded technologies. “…It utilizes a thin PI layer together with a GE developed adhesive material to create the electrical contact to the embedded components. Further, it does not require any RDL (redistribution layer) or Cu post on the component pad, which significantly reduces direct processing cost at the wafer level as well as simplifying the value chain and shortening lead time. This process flow, together with high quality patterning, gives POL technology a great potential to improve yield and reduce total cost of ownership.”

GE has worked with SavanSys to compare cost of their ePOL embedded packaging to other embedded packaging technologies. They report that ePOL has a cost advantage as the wafer post processing costs (wafer prep) are low for ePOL and additional savings are achieved in yield and production lead-time. Most other embedding technologies require a RDL layer, which has a significant impact on cost of the package, especially with large die packages. The wafer prep cost per die for RDL wafers increases further with sub-300mm wafers.

ePOL cost advantage

GE’s embedded patent portfolio
The entire GE POL technology package (which now includes the Imbera PCB technology) consists of more than 300 patents. They are available for license through GE Ventures Licensing, a GE business dedicated to the licensing of GE patents and technology. GE is committed to work with licensees to ramp-up production for GE internal as well as non GE business opportunities. 

Dr. Larry Davis, vice president and microelectronics packaging program director at GE Licensing, has stated that “Through our internally developed POL technologies and the Imbera acquisition, GE has created one of the most extensive intellectual property and technology portfolios for embedded electronic packaging in the world.”

Yole Développement - Embedded Die Patent Analysis 2012 Report

GE Ventures – Licensing - May 2014

Expanding the embedded package infrastructure
Several embedded packaging attempts have failed to penetrate to the market due to: 
- Yield challenges and/or high processing costs which led to high total cost of ownership
- Not enough technical benefit over existing packaging solutions
- Lack of infrastructure to provide packaging with commonly used business models
- Investments needed to convert existing production processes
- Fragmented supplier base with lack of standardization

In response to this, GE’s Davis states that “…GE is developing a cost effective HVM capable supply chain for embedded active components with its partners. GE is committed to transferring the GE active component embedding technology and know-how to the marketplace, partnering with industry packaging leaders to form a value chain for HVM, which GE and the rest of the industry will be able to access.” Davis further concludes that “GE has a strong technology roadmap and an extensive portfolio of key patents, with a solid corporate commitment to sustain the high level of investment in this industry-leading technology
[1] W Daum, WE Burdick and RA Fillion, “Overlay High Density Interconnect: A Chips First Multichip Module Technology”, Computer, Vol 26, Issue 4, April 1993, p 23-29



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